Establishing read operation bias schemes for 3-d pillar structure flash memory devices to overcome paired cell interference (pci)

IEICE Transactions on Electronics

Volumn E91-C, Issue 5, 2008, Pages 731-735

  Cho, Seongjae ^a   Park, Ii Han ^a   Lee, Jung Hoon ^a   Yun, Jang Gn ^a   Kim, Doo Hyun ^a   Lee, Jong Duk ^a   Shin, Hyung Cheol ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

3 D memory device; Electrical interference; Memory array; PCi (paired cell interference); Read operation

Indexed keywords

MEMORY ARCHITECTURE;

3-D NAND FLASH MEMORY; CELL INTERFERENCE; ELECTRICAL INTERFERENCE; MEMORY ARRAY; PILLAR STRUCTURE; READ OPERATION; RING CLOSERS;

FLASH MEMORY;

EID: 63749087641     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e91-c.5.731     Document Type: Article

References (5)

1. S. Cho, I.H. Park, T.H. Kim, J.H. Lee, J.D. Lee, H. Shin, and B.-G. Park, "Quantitative analysis on voltage schemes for reliable operations of a floating gate type double gate nonvolatile memory cell," J. Semiconductor Technology and Sciences, vol.5, no.3, pp. 195-203, Sept. 2005.
2. S. Cho, I.H. Park, T.H. Kim, J.S. Sim, K.-W. Song, J.D. Lee, H. Shin, and B.-G. Park, "Design and optimization of two-bit double gate nonvolatile memory cell for highly reliable operation," IEEE Trans. Nan-otechnolgy, vol.5, no.3, pp.180-185, May 2006.
3. ATLAS User's Manual, Device Simulation Software, vol.1, SILVACO International, Feb. 2000.
4. International Technology Roadmap for Semiconductors (ITRS), Process Integration, Devices, and Structures, p.23, 2006 update.
5. C. Lombardi, S. Manzini, A. Sapotiro, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.7, no.11, pp.1164-1171, Nov. 1988.