Locally-separated vertical channel SONOS flash memory (LSVC SONOS) for multi-storage and multi-level operation

IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Volumn , Issue , 2008, Pages

  Kim, Yoon ^a   Yun, Jang Gn ^a   Park, Il Han ^a   Cho, Seongjae ^a   Lee, Jung Hoon ^a   Park, Se Hwan ^a   Lee, Dong Hua ^a   Kim, Doo Hyun ^a   Lee, Gil Sung ^a   Sim, Won Bo ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ATLAS SIMULATIONS; DEVICE STRUCTURES; ELECTRICAL INTERFERENCE; FIN WIDTHS; MULTI-LEVEL; RELIABLE OPERATION; SONOS FLASH MEMORY; VERTICAL CHANNELS;

COMPUTER PERIPHERAL EQUIPMENT; FINS (HEAT EXCHANGE); INTERFACES (COMPUTER); MIXED CONVECTION; NANOELECTRONICS;

FLASH MEMORY;

EID: 77949966272     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SNW.2008.5418389     Document Type: Conference Paper

References (5)

1. ITRS road map (Semiconductor Industry Association, San Jose, 2005).
2. H.-T. Lue, et al., "Studies of the reverse read method and second-bit effect of 2-bit/cell nitride trapping device by quasitwo-dimensional mode," IEEE TED, pp.119-125, 2006. ATLAS User's Manual, SILVACOInternational, 2005.
3. C. W. Oh, et al.; "A 4-bit double SONDS memory(DSM) with 4 storage nodes per cell for ultimate multi-bit operation," VLS! Tech.dig.,pp.50-51,2006.
4. Hoon Cho, et al., "Highly Scalable Vertical Double Gate NOR Hash Memory," IDEM Tech. Dig., pp. 917-918, 2007.
5. Sukpil Kim, et al., "Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage," VLSI Tech. dig., pp. 84-85, 2006.