Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 118-119

  Choi, Byung Yong ^a   Park, Byung Gook ^a   Lee, Yong Kyu ^b   Sung, Suk Kang ^c   Kim, Tae Yong ^c   Cho, Eun Suk ^c   Cho, Hye Jin ^c   Oh, Chang Woo ^c   Kim, Sung Hwan ^c   Kim, Dong Won ^c   Lee, Choong Ho ^c   Park, Donggun ^c  

^a Seoul National University   (South Korea)

^b Stanford University   (United States)

^c SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; GATES (TRANSISTOR); RELIABILITY THEORY;

MEMORY OPERATION; NVM TECHNOLOGY; SONOS MEMORY TRANSISTOR; SPACER PROCESSES;

TRANSISTORS;

EID: 33745146170     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469235     Document Type: Conference Paper

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