Highly scalable vertical double gate NOR flash memory

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 917-920

  Cho, Hoon ^a   Kapur, Pwan ^a   Kalavade, Pranav ^b   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES;

BODY THICKNESS; NOR FLASH MEMORY; SUB-50 NM; VERTICAL DOUBLE-GATE;

FLASH MEMORY;

EID: 50249092697     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4419101     Document Type: Conference Paper

References (6)

1. B. K. Cho et al., " Technology breakthrough of body-tied FinFET for sub 50 nm NOR flash memory," VLSI Tech. pp 90-91, 2006.
2. P. Xuan et al., " FinFET SONOS flash memory for embedded applications," IDEM Tech. Dig., pp. 26.4.1-26.4.4, 2003.
3. S. Cho,, "Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation," IEEE Trans. NanoTech., vol. 5, no. 3, pp180-185, 2006.
4. K. H. Yuen,, T. Y. Man, A. C. K. Chan, and M. Chan, " A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure," IEEE Electron Device Letters, vol.24, no.8, pp. 518-520, 2003.
5. H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, "A novel spacer process for sub 25nm thick vertical MOS and its integration with planar MOS devices," IEEE Trans. Nanotech., vol. 5, no. 5, pp 554-563, 2006.
6. H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, "Geometry dependence of poly-Si oxidation and its application to self-aligned, maskless process for nano-scale vertical CMOS structures," Electro-Chemical Soc. Transactions, vol. 3, no. 2, pp 403-414, 2006.