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Volumn 152, Issue 6, 2005, Pages 1098-1102

Finite precision implementation of LDPC decoders

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; BINARY CODES; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; ERROR CORRECTION;

EID: 29144519303     PISSN: 13502425     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-com:20050205     Document Type: Conference Paper
Times cited : (31)

References (19)
  • 1
    • 84925405668 scopus 로고
    • Low density parity check codes
    • Gallager, R.G.: 'Low density parity check codes', IRE Trans. Inf. Theory, 1962, IT-8, (1), pp. 21-28
    • (1962) IRE Trans. Inf. Theory , vol.IT-8 , Issue.1 , pp. 21-28
    • Gallager, R.G.1
  • 2
    • 0031096505 scopus 로고    scopus 로고
    • Near Shannon limit performance of low density parity check codes
    • MacKay, D.J.C., and Neal, R.M.: 'Near Shannon limit performance of low density parity check codes', Electron. Lett., 1997, 33, (6), pp. 457-458
    • (1997) Electron. Lett. , vol.33 , Issue.6 , pp. 457-458
    • MacKay, D.J.C.1    Neal, R.M.2
  • 3
    • 0033099611 scopus 로고    scopus 로고
    • Good error-correcting codes based on very sparse matrices
    • MacKay, D.J.C.: 'Good error-correcting codes based on very sparse matrices', IEEE Trans. Inf. Theory, 1999, 45, (2), pp. 399-431
    • (1999) IEEE Trans. Inf. Theory , vol.45 , Issue.2 , pp. 399-431
    • MacKay, D.J.C.1
  • 4
    • 0035246127 scopus 로고    scopus 로고
    • Design of capacity-approching irregular low-density parity-check codes
    • Richardson, T.J., Shokrollahi, M.A., and Urbanke, R.L.: 'Design of capacity-approching irregular low-density parity-check codes', IEEE Trans. Inf. Theory, 2001, 47, (2), pp. 619-637
    • (2001) IEEE Trans. Inf. Theory , vol.47 , Issue.2 , pp. 619-637
    • Richardson, T.J.1    Shokrollahi, M.A.2    Urbanke, R.L.3
  • 5
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-Gb/s 1024-b, rate 1/2 low-density parity-check code decoder
    • Blanksby, A.J., and Howland, C.J.: 'A 690-mW 1-Gb/s 1024-b, rate 1/2 low-density parity-check code decoder', IEEE J. Solid-State Circuits, 2002, 37, (3), pp. 404-412
    • (2002) IEEE J. Solid-state Circuits , vol.37 , Issue.3 , pp. 404-412
    • Blanksby, A.J.1    Howland, C.J.2
  • 6
    • 0742286682 scopus 로고    scopus 로고
    • High throughput LDPC decoders
    • Mansour, M.M., and Shanbhag, N.R.: 'High throughput LDPC decoders', IEEE Trans. VLSI Syst., 2003, 11, (6), pp. 976-996
    • (2003) IEEE Trans. VLSI Syst. , vol.11 , Issue.6 , pp. 976-996
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 8
    • 0037633661 scopus 로고    scopus 로고
    • LDPC code construction with flexible hardware implementation
    • Anchoarage, USA, May
    • Hocevar, D.E.: 'LDPC code construction with flexible hardware implementation'. Proc. IEEE Int. Conf. on Communications 2003, (ICC 2003), Anchoarage, USA, May 2003, Vol. 4, pp. 2708-2712
    • (2003) Proc. IEEE Int. Conf. on Communications 2003, (ICC 2003) , vol.4 , pp. 2708-2712
    • Hocevar, D.E.1
  • 10
    • 0016037512 scopus 로고
    • Optimal decoding of linear codes for minimizing symbol error rate
    • Bahl, L., Cocke, J., Jelinek, F., and Raviv, J.: 'Optimal decoding of linear codes for minimizing symbol error rate', IEEE Trans. Inf. Theory, 1974, 20, (3), pp. 284-287
    • (1974) IEEE Trans. Inf. Theory , vol.20 , Issue.3 , pp. 284-287
    • Bahl, L.1    Cocke, J.2    Jelinek, F.3    Raviv, J.4
  • 11
    • 29144488091 scopus 로고    scopus 로고
    • Flexible hardware for wireless communications: A case of study
    • Poznan, Poland, April
    • Masera, G.: 'Flexible hardware for wireless communications: a case of study'. Proc. URSI XI National Symp. of Radio Science, Poznan, Poland, April 2005
    • (2005) Proc. URSI XI National Symp. of Radio Science
    • Masera, G.1
  • 13
    • 0242578159 scopus 로고    scopus 로고
    • CMOS VLSI implementation of a low-power logarithmic converter
    • Abed, K.H., and Siferd, R.E.: 'CMOS VLSI implementation of a low-power logarithmic converter', IEEE Trans. Comput., 2003, 52, (11), pp. 1421-1433
    • (2003) IEEE Trans. Comput. , vol.52 , Issue.11 , pp. 1421-1433
    • Abed, K.H.1    Siferd, R.E.2
  • 14
    • 0000980875 scopus 로고
    • Computer multiplication and division using binary logarithms
    • Mitchell, J.N. Jr.: 'Computer multiplication and division using binary logarithms', IRE Trans. Electron. Comput., 1962, 11, pp. 512-517
    • (1962) IRE Trans. Electron. Comput. , vol.11 , pp. 512-517
    • Mitchell Jr., J.N.1
  • 15
    • 29144459072 scopus 로고    scopus 로고
    • Nov. Release of 2001-11-18. [Online]
    • Neal, R.: (2001, Nov.) LDPC CoDec C Code package. Release of 2001-11-18. [Online]. Available: http://www.cs.toronto.edu/~radford/ ldpc.software.html
    • (2001) LDPC CoDec C Code Package
    • Neal, R.1
  • 18
  • 19
    • 29144482956 scopus 로고    scopus 로고
    • A synthesizable IP Core for DVB-S2 LDPC code decoding
    • Mar.
    • Kienle, F., Brack, T., and Wehn, N.: 'A synthesizable IP Core for DVB-S2 LDPC code decoding'. Proc. DATE 2005, Mar. 2005, pp. 100-105
    • (2005) Proc. DATE 2005 , pp. 100-105
    • Kienle, F.1    Brack, T.2    Wehn, N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.