Implementing LDPC decoding on network-on-chip

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 134-137

  Theocharides, T ^a   Link, G ^a   Vijaykrishnan, N ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE RATES; DECODER ARCHITECTURE; ERROR CORRECTING CODES; LOW-DENSITY PARITY CHECK (LDPC) CODES;

CHANNEL CAPACITY; CODES (SYMBOLS); COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTATIONAL COMPLEXITY; DECODING; OPTIMIZATION; WIRELESS TELECOMMUNICATION SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 27944498512     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.109     Document Type: Conference Paper

References (12)

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