Interconnection framework for high-throughput, flexible LDPC decoders

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 2, Issue , 2006, Pages

  Quaglio, Federico ^a   Vacca, Fabrizio ^a   Castellano, Cristiano ^a   Tarable, Alberto ^a   Masera, Guido ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION COMPLEXITY; INTERCONNECTION FRAMEWORK; LDPC DECODERS;

CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; DECODING; THROUGHPUT;

INTERCONNECTION NETWORKS;

EID: 34047111317     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269064     Document Type: Conference Paper

References (12)

1. R. G. Gallager, "Low Density Parity Check Codes," IRE Trans. Information Theory, vol. IT-8, no. 1, pp. 21-28, 1962.
2. D. J. C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electron. Lett., vol. 33, no. 6, pp. 457-458, 1997.
3. D. J. C. MacKay, "Good Error-Correcting Codes Based on Very Sparse Matrices," IEEE Trans. Inform. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.
4. T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of Capacity-Approching Irregular Low-Density Parity-Check Codes," IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.
5. A. J. Blanksby and C. J. Rowland, "A 690-mW 1-Gb/s 1024-b, Rate 1/2 Low-Density Parity-Check Code Decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
6. M. M. Mansour and N. R. Shanbhag, "High Through-put LDPC Decoders," IEEE Trans. VLSI Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003.
7. T. Zhang and K. K. Parhi, "Joint Code and Decoder Design for Implementation-Oriented (3,k)-regular LDPC Codes," in Proc. Asilomar Conference on Signals, Systems and Computers, vol. 2, Nov. 2001, pp. 1232-1236.
8. D. E. Hocevar, "LDPC code construction with flexible hardware implementation," in Proc. IEEE Int. Conf. on Communications 2003, (ICC 2003), vol. 4, Anchoarage, USA, May 2003, pp. 2708-2712.
9. A. Tarable, S. Benedetto, and G. Montorsi, "Mapping interleaver laws to parallel turbo and LDPC decoders architectures," IEEE Trans. Inform. Theory, vol. 50, no. 9, pp. 2002-2009, Sept. 2004.
10. V. E. Benes, "Optimal Rearrangeable Multistage Connecting Networks," Bell System Technical Journal, vol. 43, pp. 1641-1656, 1964.
11. F. Quaglio, F. Vacca, and G. Masera, "Low Complexity, Flexible LDPC Decoders," Proc. 14th IST Mobile Summit 2005, June 2005.
12. F. Kienle, M. J. Thul, and N. Wehn, "Implemntation Issue of Scalable LDPC-Decoders," in Proc. 3rd Int. Symp. on Turbo Codes & Related Topics, Brest, France, Sept. 2003, pp. 291-294.