A binary tree architecture for Application Specific Network on Chip (ASNOC) design

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 2, Issue , 2004, Pages 877-880

  Jeang, Yuan Long ^a   Huang, Win Hsien ^a   Fang, Wei Feng ^a  

^a NATIONAL KAOHSIUNG UNIVERSITY OF APPLIED SCIENCES   (Taiwan)

Author keywords

Binary tree architecture; Globally asynchronous network; Locally synchronous bus; Network on chip; System on a chip; Wormhole routing

Indexed keywords

ADDERS; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PRODUCT DESIGN; ROUTERS; SWITCHING; SYNCHRONIZATION;

BINARY TREE ARCHITECTURE; GLOBALLY ASYNCHRONOUS NETWORK; LOCALLY SYNCHRONOUS BUS; NETWORK ON CHIP; SYSTEM-ON-CHIP; WORMHOLE ROUTING;

TREES (MATHEMATICS);

EID: 21644435835     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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