Mapping interleaving laws to parallel turbo and LDPC decoder architectures

IEEE Transactions on Information Theory

Volumn 50, Issue 9, 2004, Pages 2002-2009

  Tarable, Alberto ^a   Benedetto, Sergio ^a   Montorsi, Guido ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA COMMUNICATION SYSTEMS; DATA STORAGE EQUIPMENT; ITERATIVE METHODS; OPTIMIZATION; TURBO CODES;

LOW DENSITY PARITY CHECK CODES; MEMORY MAPPING; PARALLEL IMPLEMENTATION;

DECODING;

EID: 4544260488     PISSN: 00189448     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIT.2004.833353     Document Type: Article

References (19)

1. S. M. Aji and R. J. McEliece, "The generalized distributive law," IEEE Trans. Inform. Theory, vol. 46, pp. 325-343, Mar. 2000.
2. L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inform. Theory, vol. IT-20, pp. 284-287, Mar. 1974.
3. S. Benedetto, D. Divsalar, G. Montorsi, and E Pollara, "Serial concatenation of interleaved codes: Performance analysis, design, and iterative decoding," Electron. Lett., vol. 32, pp. 1186-1188, June 1996.
4. S. Benedetto, "Soft-input soft-output modules for the construction and distributed iterative decoding of code networks," Europ. Trans. Telecommun., vol. 9, no. 2, Mar.-Apr. 1998.
5. S. Benedetto and G. Montorsi, "Unveiling turbo codes: Some results on parallel concatenated coding schemes," IEEE Trans. Inform. Theory, vol. 42, pp. 409-428, Mar. 1996.
6. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correction coding and decoding: Turbo-codes," in Proc. 1993 Int. Conf. on Communications (ICC '93), 1993, pp. 1064-1070.
7. A. J. Blanksby and C. J. Howland, "Parallel decoding architectures for low density parity check codes," in Proc. IEEE Int Symp. Circuits and Systems 2001 (ISCASO1), vol. 4, Sydney, Australia, May 2001, pp. 742-745.
8. R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, 1963.
9. A. Giulietti, L. Van der Perre, and A. Strum, "Parallel turbo coding interleavers: Avoiding collisions in accesses to storage elements," Electron. Lett., vol. 38, pp. 232-234, Feb. 2002.
10. D. Gnaedig, E. Boutillon, M. Jézéquel, V. C. Gaudet, and P. G. Gulak, "On multiple slice turbo codes," in Proc. 3rd Symp. Turbo Codes and Related Topics, Brest, France, Sept. 2003, pp. 343-346.
11. J. Kwak and K. Lee, "Design of dividable interleaver for parallel decoding in turbo codes," Electron. Lett., vol. 38, pp. 1362-1364, Oct. 2002.
12. R. J. McEliece, D. J. C. MacKay, and J.-F Cheng, "Turbo decoding as an instance of Pearl's belief propagation algorithm," IEEE Trans. Select. Areas Commun., vol. 16, pp. 140-152, Feb.-1998..
13. D. J. C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electron. Lett., vol. 32, pp. 1645-1646, Aug. 1996.
14. M. M. Mansour and N. R. Shanbhag, "Memory-efficient turbo decoder architectures for LDPC codes," in Proc. IEEE Workshop on Signal Processing Systems 2002 (SIPS02), San Diego, CA, Oct. 2002, pp. 159-164.
15. A. Nimbalker,.T K. Blankenship, B. Classon, T. E. Fuja, and D. J. Costello Jr., "Inter-window shuffle interleavers for high throughput turbo decoding," in Proc. 3rd Syrup. Turbo Codes and Related Topics, Brest, France, Sept. 2003, pp. 355-358.
16. A. Selvarathinam, G. Choi, K. Narayanan, A. Prabhakar, and E. Kim, "A massively scaleable decoder architecture for low-density parity-check codes," in Proc. IEEE Int Syrup. Circuits and Systems 2003 (ISCAS03), vol. 2, Bangkok, Thailand, May 2003, pp. 61-64.
17. M. J. Thul, N. Wehn, and L. P. Rao, "Enabling high-speed turbo-decoding through concurrent interleaving," in Proc. IEEE Int Symp. Circuits and Systems 2002 (ISCAS02), vol. 1, Scottsdale, AZ, May 2002, pp. 897-900.
18. F. Verdier and D. Declercq, "A LDPC parity-check matrix construction for parallel hardware decoding," in Proc. 3rd Symp. Turbo Codes and Related Topics, Brest, France, Sept. 2003, pp. 235-238.
19. A. Tarable and S. Benedetto, "Mapping interleaving laws to parallel turbo decoder architectures," IEEE Comm. Lett., vol. 8, pp. 162-164, Mar. 2004.