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1
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84893641728
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A decade of reconfigurable computing: A visionary retrospective
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Mar.
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H. Reiner, "A decade of reconfigurable computing: A visionary retrospective," in Proc. Des. Autom. Test Eur. Conf., Mar. 2001, pp. 642-649.
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(2001)
Proc. Des. Autom. Test Eur. Conf.
, pp. 642-649
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Reiner, H.1
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2
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84884681913
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KressArray Xplorer: A new CAD environment to optimize reconfigurable datapath array architectures
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Jan.
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H. Reiner, M. Herz, T. Hoffmann, and U. Nageldinger, "KressArray Xplorer: A new CAD environment to optimize reconfigurable datapath array architectures," in Proc. Asia South Pacific Des. Autom. Conf., Jan. 2000, pp. 163-168.
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(2000)
Proc. Asia South Pacific Des. Autom. Conf.
, pp. 163-168
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Reiner, H.1
Herz, M.2
Hoffmann, T.3
Nageldinger, U.4
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3
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3042515351
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Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: A case study
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Mar.
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M. Bingfeng, V. Serge, V. Diederik, and L. Rudy, "Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: A case study," in Proc. Des. Autom. Test Eur. Conf., Mar. 2004, pp. 1224-1229.
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(2004)
Proc. Des. Autom. Test Eur. Conf.
, pp. 1224-1229
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Bingfeng, M.1
Serge, V.2
Diederik, V.3
Rudy, L.4
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4
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84925329195
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Analysis of the performance of coarse-grain reconfigurable architectures with different processing element configurations
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presented at the, San Diego, CA, Dec.
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B. Nikhil, G. Sumit, D. D. Nikil, and N. Alex, "Analysis of the performance of coarse-grain reconfigurable architectures with different processing element configurations," presented at theWorkshop Appl. Specific Process., San Diego, CA, Dec. 2003.
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(2003)
Workshop Appl. Specific Process.
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Nikhil, B.1
Sumit, G.2
Nikil, D.D.3
Alex, N.4
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5
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73249114650
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Energy-aware interconnect-exploration of coarse-grained reconfigurable processors
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presented at the, New York, Sep.
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L. Andy, R. Praveen, and J. Murali, "Energy-aware interconnect-exploration of coarse-grained reconfigurable processors," presented at the Workshop Appl. Specific Process., New York, Sep. 2005.
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(2005)
Workshop Appl. Specific Process.
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Andy, L.1
Praveen, R.2
Murali, J.3
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6
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73249143648
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Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs
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presented at the, Washington, DC, Apr.
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Z. Hui, W. Marlene, G. Varghese, and R. Jan, "Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs," presented at the VLSI, Washington, DC, Apr. 1999.
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(1999)
VLSI
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Hui, Z.1
Marlene, W.2
Varghese, G.3
Jan, R.4
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7
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12444252997
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Mapping of regular nested loop programs to coarse-grained reconfigurable arrays - Constraints and methodology
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Apr.
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H. Frank, D. Hritam, and T. Jurgen, "Mapping of regular nested loop programs to coarse-grained reconfigurable arrays - Constraints and methodology," in Proc. IEEE Int. Parallel Distrib. Process. Symp., Apr. 2004, p. 148a.
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(2004)
Proc. IEEE Int. Parallel Distrib. Process. Symp.
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Frank, H.1
Hritam, D.2
Jurgen, T.3
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8
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73249138295
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(CECS), Univ. California Irvine, Irvine, Tech. Rep.
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L. Jong-eun, C. Kiyoung, and D. D. Nikil, Mapping loops on coarse-grained reconfigurable architectures using memory operation sharing Center Embedded Comput. Syst. (CECS), Univ. California Irvine, Irvine, Tech. Rep. 02-34, 2002.
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Mapping Loops on Coarse-grained Reconfigurable Architectures Using Memory Operation Sharing Center Embedded Comput. Syst.
, pp. 02-34
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Jong-Eun, L.1
Kiyoung, C.2
Nikil, D.D.3
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9
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0242696249
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An algorithm for mapping loops onto coarse-grained reconfigurable architectures
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Jul.
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J.-E. Lee, K. Choi, and N. D. Dutt, "An algorithm for mapping loops onto coarse-grained reconfigurable architectures," ACM Sigplan Notices, vol.38, no.7, pp. 183-188, Jul. 2003.
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ACM Sigplan Notices
, vol.38
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, pp. 183-188
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Lee, J.-E.1
Choi, K.2
Dutt, N.D.3
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10
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0037253010
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Compilation approach for coarsegrained reconfigurable architectures
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Jan.
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J.-E. Lee, K. Choi, and N. D. Dutt, "Compilation approach for coarsegrained reconfigurable architectures," IEEE Des. Test Comput., vol.20, no.1, pp. 26-33, Jan. 2003.
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(2003)
IEEE Des. Test Comput.
, vol.20
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, pp. 26-33
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Lee, J.-E.1
Choi, K.2
Dutt, N.D.3
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11
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4544332232
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Regular mapping for coarse-grained reconfigurable architectures
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May
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F. Hanning, H. Dutta, and J. Teich, "Regular mapping for coarse-grained reconfigurable architectures," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., May 2004, pp. 57-60.
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(2004)
Proc. IEEE Int. Conf. Acoust., Speech, Signal Process.
, pp. 57-60
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Hanning, F.1
Dutta, H.2
Teich, J.3
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12
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0034187952
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MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
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DOI 10.1109/12.859540
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H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho, "Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications," IEEE Trans. Comput., vol.49, no.5, pp. 465-481, May 2000. (Pubitemid 30897141)
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IEEE Transactions on Computers
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Singh, H.1
Lee, M.-H.2
Lu, G.3
Kurdahi, F.J.4
Bagherzadeh, N.5
Chaves Filho, E.M.6
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13
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84942036117
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Architecture, memory and interface technology integration of an industrial/academic configurable system-onchip (CSoC)
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presented at the, Washington, DC
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J. Becker and M. Vorbach, "Architecture, memory and interface technology integration of an industrial/academic configurable system-onchip (CSoC)," presented at the IEEE Comput. Soc. Annu. Symp. VLSI, Washington, DC, 2003.
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(2003)
IEEE Comput. Soc. Annu. Symp. VLSI
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Becker, J.1
Vorbach, M.2
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14
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20844445313
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Implementing and evaluating stream applications on the dynamically reconfigurable processor
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Apr.
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N. Suzuki, S.Kurotaki, M. Suzuki, N. Kaneko, Y.Yamada, K. Deguchi, Y. Hasegawa, H. Amano, K. Anjo, M. Motomura, K.Wakabayashi, T. Toi, and T. Awashima, "Implementing and evaluating stream applications on the dynamically reconfigurable processor," in Proc. Field-Program. Custom Comput. Mach., Apr. 2004, pp. 328-329.
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(2004)
Proc. Field-Program. Custom Comput. Mach.
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Suzuki, N.1
Kurotaki, S.2
Suzuki, M.3
Kaneko, N.4
Yamada, Y.5
Deguchi, K.6
Hasegawa, Y.7
Amano, H.8
Anjo, K.9
Motomura, M.10
Wakabayashi, K.11
Toi, T.12
Awashima, T.13
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15
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33746868352
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Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes
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Aug.
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F.-J. Vererdas, M. Scheppler, W. Moffat, and B. Mei, "Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes," in Proc. Int. Conf. Field Program. Logic Appl., Aug. 2005, pp. 106-111.
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Proc. Int. Conf. Field Program. Logic Appl.
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Vererdas, F.-J.1
Scheppler, M.2
Moffat, W.3
Mei, B.4
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16
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33747033288
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Design and evaluation of coarse-grained reconfigurable architecture
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Oct.
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Y. Kim, C. Park, S. Kang, H. Song, J. Jung, and K. Choi, "Design and evaluation of coarse-grained reconfigurable architecture," in Proc. Int. SoC Des. Conf., Oct. 2004, pp. 227-230.
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Proc. Int. SoC Des. Conf.
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Kim, Y.1
Park, C.2
Kang, S.3
Song, H.4
Jung, J.5
Choi, K.6
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17
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33646918066
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Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization
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DOI 10.1109/DATE.2005.260, 1395521, Proceedings - Design, Automation and Test in Europe, DATE '05
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Y. Kim, M. Kiemb, C. Park, J. Jung, and K. Choi, "Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization," in Proc. Des. Autom. Test Eur. Conf.,Mar. 2005, pp. 12-17. (Pubitemid 44234568)
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Proceedings -Design, Automation and Test in Europe, DATE '05
, vol.I
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Kim, Y.1
Kiemb, M.2
Park, C.3
Jung, J.4
Choi, K.5
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18
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34247258357
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Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture
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Oct.
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Y. Kim, I. Park, K. Choi, and Y. Paek, "Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture," in Proc. Int. Symp. Low Power Electron. Des., Oct. 2006, pp. 310-315.
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Proc. Int. Symp. Low Power Electron. Des.
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Kim, Y.1
Park, I.2
Choi, K.3
Paek, Y.4
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19
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0036045954
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PipeRench:Avirtualized programmable datapath in 0.18 micron technology
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May
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H. Schmit, D. Whelihan, A. Tsai, M. Moe, B. Levine, and R. R. Tsai, "PipeRench:Avirtualized programmable datapath in 0.18 micron technology," in Proc. IEEE Custom Integr. Circuits Conf., May 2002, pp. 63-66.
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Proc. IEEE Custom Integr. Circuits Conf.
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Schmit, H.1
Whelihan, D.2
Tsai, A.3
Moe, M.4
Levine, B.5
Tsai, R.R.6
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20
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84942851882
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A quantitative analysis of reconfigurable coprocessors for multimedia applications
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Apr.
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Proc. IEEE Symp. FPGAs Custom Comput. Mach.
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Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
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Aug.
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M. Lanuzza, M. Margala, and P. Corsonello, "Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2005, pp. 161-166.
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Proc. Int. Symp. Low Power Electron. Des.
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Lanuzza, M.1
Margala, M.2
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Synthesizable reconfigurable array targeting distributed arithmetic for system-on-chip applications
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Apr.
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S. Khawam, T. Arslan, and F. Westall, "Synthesizable reconfigurable array targeting distributed arithmetic for system-on-chip applications," in Proc. IEEE Int. Parallel Distrib. Process. Symp., Apr. 2004, pp. 150-150
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Proc. IEEE Int. Parallel Distrib. Process. Symp.
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Khawam, S.1
Arslan, T.2
Westall, F.3
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23
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33746166316
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Low power coarse-grained reconfigurable instruction set processor
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Sep.
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F. Barat, M. Jayapala, T. V. A. H. Corporaal, G. Deconinck, and R. Lauwereins, "Low power coarse-grained reconfigurable instruction set processor," in Proc. Int. Conf. Field Program. Logic Appl., Sep. 2003, pp. 230-239.
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Proc. Int. Conf. Field Program. Logic Appl.
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Barat, F.1
Jayapala, M.2
Corporaal, T.V.A.H.3
Deconinck, G.4
Lauwereins, R.5
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25
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73249117557
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Available
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ARM Corporation [Online]. Available: http://www.arm.com/arm/AMBA
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26
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73249143443
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[Online]. Available
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Synopsys Corporation [Online]. Available: http://www.synopsys.com
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27
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73249146614
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[Online]. Available
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Taiwan Semi Manufacturing Company Ltd. [Online]. Available: http://www.tsmc.com
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28
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73249144081
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[Online]. Available
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Model Technology Corporation [Online]. Available: http://www.model.com
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