Regular mapping for coarse-grained reconfigurable architectures

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 2004, Pages

  Hannig, Frank ^a   Dutta, Hritam ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DEVICES; OPTIMIZATION; PROGRAM COMPILERS; PROGRAMMABLE LOGIC CONTROLLERS;

AFFINE TRANSFORMATION; COARSE-GRAINED RECONFIGURABLE ARCHITECTURES; CONTROL GENERATION; SEMICONDUCTOR TECHNOLOGY;

COMPUTER SCIENCE;

EID: 4544332232     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. P. Feautrier, "Automatic Parallelization in the Polytope Model," Tech. Rep. 8, Laboratoire PRiSM, Université des Versailles St-Quentin en Yvelines, Versailles Cedex, June 1996.
2. P. Schaumont, I. Verbauwhede, K. Keutzer, and M. Sarrafzadeh, "A Quick Safari Through the Reconfiguration Jungle," in 38th Design Automation Conference, Las Vegas, NV, June 2001, pp. 172-177.
3. R. Hartenstein, "A Decade of Reconfigurable Computing: A Visionary Retrospective," in Proceedings of Design, Automation and Test in Europe, Munich, Germany, Mar. 2001, pp. 642-649.
4. Elixent Ltd., www.elixent.com
5. M. Motomura, "A Dynamically Reconfigurable Processor Architecture," in Microprocessor Forum, CA, 2002.
6. V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, "PACT XPP - A Self-Reconfigurable Data Processing Architecture," The Journal of Supercomputing, vol. 26, no. 2, pp. 167-184, 2003.
7. Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood, "Hardware-software Co-Design of Embedded Reconfigurable Architectures," in 37th Design Automation Conference, Los Angeles, CA, June 2000, pp. 507-512.
8. PARO Design System Project, www12.informatik.uni-erlangen.de/reaearch/ paro
9. G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Böhm, and J. Hammes, "Automatic Compilation to a Coarse-grained Reconfigurable System-on-Chip," ACM Trans, on Embedded Computing Systems, to appear November 2003.
10. H. Singh, M.-H. Lee, G. Lu, N. Bagherzadeh, F.J. Kurdahi, and E.M. Chaves Filho, "Morphosys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications," IEEE Transactions on Computers, vol. 49, no. 5, pp. 465-481, 2000.
11. J. Lee, K. Choi, and N. Dutt, "An Algorithm for Mapping Loops onto Coarse-grained Reconfigurable Architectures," in Languages, Compilers, and Tools for Embedded Systems (LCTES'03), San Diego, CA, June 2003, pp. 183-188.
12. F. Hannig and J. Teich, "Design Space Exploration for Massively Parallel Processor Arrays," in Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings, V. Malyshkin, Ed., Novosibirsk, Russia, Sept. 2001, vol. 2127 of Lecture Notes in Computer Science (LNCS), pp. 51-65.
13. F. Hannig and J. Teich, "Energy Estimation of Nested Loop Programs," in Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), Winnipeg, Manitoba, Canada, Aug. 2002.
14. J. Teich and L. Thiele, "Exact Partitioning of Affine Dependence Algorithms," in Embedded Processor Design Challenges, E.F. Deprettere, J. Teich, and S. Vassiliadis, Eds., Mar. 2002, vol. 2268 of Lecture Notes in Computer Science (LNCS), pp. 135-153.
15. PACT XPP Technologies, XPP64-A1 Reconfigurable Processor - Datasheet, Munich, Germany, 2003.
16. F. Gunnarsson, C. Hansson, D. Johnsson, and B. Svensson, "Implementing High Speed Matrix Processing on a Reconfigurable Parallel Dataflow Processor," in Second International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02), Las Vegas, NV, June 2002, pp. 74-80.