Synthesizable reconfigurable array targeting distributed arithmetic for system-on-chip applications

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 2051-2058

  Khawam, Sami ^a   Arslan, Tughrul ^a,b   Westall, Fred ^c  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

^b INSTITUTE FOR SYSTEM LEVEL INTEGRATION   (United Kingdom)

^c Epson Scotland Design Centre   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARRAYS; BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; FILTRATION; MOBILE TELECOMMUNICATION SYSTEMS; MULTIMEDIA SYSTEMS; OPTIMIZATION; PROGRAM PROCESSORS;

DISTRIBUTED ARITHMETIC (DA) IMPLEMENTATIONS; MOBILE DEVICES; POWER CONSUMPTION; SYSTEM-ON-CHIP APPLICATIONS;

DIGITAL ARITHMETIC;

EID: 12444275637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Khawam S., Arslan T., Westall F., "Embedded reconfigurable array targeting motion estimation applications", Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (ISCAS'03), May 2003, Vol. 2, Page(s): 760-763
2. Hounsell B.I.; Arslan, T., "An embedded programmable core for the implementation of high performance digital filters", ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, 12-15 Sept. 2001, Page(s): 169-174
3. White, S.A, "Applications of distributed arithmetic to digital signal processing: a tutorial review", ASSP Magazine, IEEE, Volume: 6 Issue: 3, Jul 1989, Page(s): 4-19
4. Abnous A., Rabaey J.M., "Ultra-low-power domain-specific multimedia processors", IEEE VLSI Signal Processing, 1996
5. Bryant I., Tanurhan Y., "The Actel Embeddable FPGA Core", Actel Corporation, 2001
6. Burleson, W.; Jain, P.; Venkatraman, S., "Dynamically parameterized architectures for power-aware video coding: motion estimation and DCT, Digital and Computational Video", 2001 Proceedings Second International Workshop on DVC, Vol., 2001, Pages: 4-12
7. Sungwook Yu; Swartzlander, E.E., Jr., "DCT implementation with distributed arithmetic", IEEE Transactions on Computers, Vol. 50 Is. 9, Sept. 2001
8. Ahmed N., Natarjan T., Rao K.R., "Discrete Cosine Transform", IEEE Trans. On Computers, Vol. C-23, No. 1, pp.90-93, December 1984
9. Yi Yang; Chunyan Wang; Omair Ahmad, M.; Swamy, M.N.S., "An on-line CORDIC based 2-D IDCT implementation using distributed arithmetic", Sixth International Symposium on Signal Processing and its Applications,. 2001, Vol. 1
10. Kyeounsoo Kim; Jong-Seog Koh, "An area efficient DCT architecture for MPEG-2 video encoder" ,Consumer Electronics, IEEE Transactions on, vol. 45 Issue: 1, Feb. 1999
11. Wilton, S.J.E.; "Embedded memory in FPGAs: recent research results", Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on, 1999, Page(s): 292-296
12. Rose J., Brown S., "Flexibility of interconnection structures for field-programmable gate arrays", Solid-State Circuits, IEEE Journal of, Vol.26, Iss.3, 1990, Pages: 277-282
13. George V., Zhang H., Rabaye J, "The design of low energy FPGA, Proceedings", 1999 International Symposium on Low Power Electronics and Design, pp. 188-193. 1999
14. Betz V., Rose J., and Marquardt A., "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, 1999. ISBN 0-7923-8460-1
15. Xilinx, The Programmable Logic Data Book. Xilinx Inc., 2001
16. Kafafi N., Bozman K., Wilton S.J.E, "Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores", ACM International Symposium on FPGA, Monterey, CA, Feb 2003.
17. Leijten-Nowak, K.; Katoch, A, "Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13μm", ASIC/SOC Conference, 2002. 15th Annual IEEE International, pp. 3-7
18. Marshall A., Stansfield T., Kostamov I., Vuillemin J., Hutchings B., "A Reconfigurable Arithmetic Array for Multimedia Applications", ACM/SIGDA International Symposium on FPGAs, Monterey, Feb 1999
19. eASIC, "eASIC 0.13um Core", www.easic.com