Enabling technologies for 3D chip stacking

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2008, Pages 76-78

  Leduc, Patrick ^a   Di Cioccio, Léa ^a   Charlet, Barbara ^a   Rousseau, Maxime ^a   Assous, Myriam ^a   Bouchu, David ^a   Roule, Anne ^a   Zussy, Marc ^a   Gueguen, Pierric ^a   Roman, Antonio ^a   Rozeau, Olivier ^a   Heitzmann, Michel ^a   Nieto, Jean Pierre ^a   Vandroux, Laurent ^a   Haumesser, Paul Henri ^a   Quenouillère, Rémi ^a   Toffoli, Alain ^a   Sixt, Pierre ^a   Maitrejean, Sylvain ^a   Clavelier, Laurent ^a   Sillon, Nicolas ^a   more..

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; SECURITY SYSTEMS; SELF ASSEMBLY; TECHNOLOGY;

3-D INTEGRATION; CHIP STACKING; DIRECT BONDING; ENABLING TECHNOLOGIES; HIGH-DENSITY; INTERNATIONAL SYMPOSIUM; KEY TECHNOLOGIES; PRELIMINARY DESIGN; SELF- ASSEMBLIES; SPICE SIMULATIONS; SUBSTRATE NOISE; VLSI TECHNOLOGIES; WAFER-THINNING PROCESS;

WAFER BONDING;

EID: 49049102928     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2008.4530806     Document Type: Conference Paper

References (12)

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