INVISIFENCE: Performance-transparent memory ordering in conventional multiprocessors

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 233-244

  Blundell, Colin ^a   Martin, Milo M K ^a   Wenisch, Thomas F ^b  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Memory consistency; Parallel programming

Indexed keywords

ATOMIC OPERATION; CACHE COHERENCE PROTOCOLS; CONSISTENCY ENFORCEMENT; CONSISTENCY MODEL; INVALIDATION MECHANISM; MEMORY CONSISTENCY; MEMORY CONSISTENCY MODELS; MEMORY ORDERING; MODES OF OPERATION; ORDERED MODELS; ORDERING CONSTRAINTS; PERFORMANCE PENALTIES; PROCESSOR CORES; STORAGE REQUIREMENTS;

ATOMS; COMPUTERS; FENCES; MACHINE DESIGN; MULTIPROCESSING SYSTEMS; PARALLEL PROGRAMMING; RETAIL STORES;

COMPUTER ARCHITECTURE;

EID: 70450248788     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555785     Document Type: Conference Paper

References (35)

1. S. V. Adve and K. Gharachorloo. Shared Memory Consistency Models: A Tutorial. IEEE Computer, 29(12):66-76, Dec. 1996.
2. L. Baugh, N. Neelakantam, and C. Zilles. Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory. In Proceedings of the 35th Annual International Symposium on Computer Architecture, pages 115-126, June 2008.
3. R. Bhargava and L. K. John. Issues in the Design of Store Buffers in Dynamically Scheduled Processors. In Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 76-87, 2000.
4. H. Cain and M. Lipasti. Memory Ordering: A Value-Based Approach. In Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004.
5. L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas. BulkSC: Bulk Enforcement of Sequential Consistency. In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007.
6. L. Ceze, J. M. Tuck, C. Cascaval, and J. Torrellas. Bulk Disambiguation of Speculative Threads in Multiprocessors. In Proceedings of the 33rd Annual International Symposium on Computer Architecture, June 2006.
7. H. Chafi, J. Casper, B. D. Carlstrom, A. McDonald, C. C. Minh, W. Baek, C. Kozyrakis, and K. Olukotun. A Scalable, Non-blocking Approach to Transactional Memory. In Proceedings of the 13th Symposium on High-Performance Computer Architecture, Feb. 2007.
8. Y. Chou, L. Spracklen, and S. G. Abraham. Store Memory-Level Parallelism Optimizations for Commercial Applications. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, pages 183-196, Nov. 2005.
9. A. Cristal, O. J. Santana, M. Valero, and J. F. Martinez. Toward Kilo-Instruction Processors. ACM Transactions on Architecture and Code Optimization, 1(4), Dec. 2004.
10. M. Galluzzi, E. Vallejo, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith, and M. Valero. Implicit Transactional Memory in Kilo-Instruction Multiprocessors. In Asia-Pacific Computer Systems Architecture Conference, pages 339-353, 2007.
11. M. J. Garzarán, M. Prvulovic, J. M. Llabería, V. Vińals, L. Rauchwerger, and J. Torrellas. Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. In Proceedings of the Ninth Symposium on High-Performance Computer Architecture, Feb. 2003.
12. K. Gharachorloo, A. Gupta, and J. Hennessy. Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 245-257, Apr. 1991.
13. K. Gharachorloo, A. Gupta, and J. Hennessy. Two Techniques to Enhance the Performance of Memory Consistency Models. In Proceedings of the International Conference on Parallel Processing, volume I, pages 355-364, Aug. 1991.
14. C. Gniady and B. Falsafi. Speculative Sequential Consistency with Little Custom Storage. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 179-188, Sept. 2002.
15. C. Gniady, B. Falsafi, and T. Vijaykumar. Is SC + ILP = RC? In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 162-171, May 1999.
16. S. Gopal, T. Vijaykumar, J. E. Smith, and G. S. Sohi. Speculative Versioning Cache. In Proceedings of the 4th Symposium on High-Performance Computer Architecture, Feb. 1998.
17. L. Hammond, B. D. Carlstrom, V. Wong, B. Hertzberg, M. Chen, C. Kozyrakis, and K. Olukotun. Programming with Transactional Coherence and Consistency (TCC). In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 1-13, Oct. 2004.
18. L. Hammond, M. Willey, and K. Olukotun. Data Speculation Support for a Chip Multiprocessor. In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 58-69, Oct. 1998.
19. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In Proceedings of the 31st Annual International Symposium on Computer Architecture, pages 102-113, June 2004.
20. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 289-300, May 1993.
21. M. D. Hill. Multiprocessors Should Support Simple Memory Consistency Models. IEEE Computer, 31(8):28-34, Aug. 1998.
22. M. Kirman, N. Kirman, and J. F. Martinez. Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2005.
23. J. Martinez, J. Renau, M. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed Early Resource Recycling in Out-of-Order Microprocessors. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2002.
24. J. F. Martinez and J. Torrellas. Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2002.
25. N. Neelakantam, R. Rajwar, S. Srinivas, U. Srinivasan, and C. Zilles. Hardware Atomicity for Reliable Software Speculation. In Proceedings of the 34th Annual International Symposium on Computer Architecture, pages 174-185, June 2007.
26. V. S. Pai, P. Ranganathan, S. V. Adve, and T. Harton. An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 12-23, Oct. 1996.
27. R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Proceedings of the 34th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2001.
28. P. Ranganathan, V. S. Pai, and S. V. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proceedings of the Ninth ACM Symposium on Parallel Algorithms and Architectures, pages 199-210, June 1997.
29. A. Roth. Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. In Proceedings of the 32nd Annual International Symposium on Computer Architecture, pages 458-468, June 2005.
30. J. M. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy. POWER4 System Microarchitecture. IBM Journal of Research and Development, 46(1), 2002.
31. O. Trachsel, C. von Praun, and T. R. Gross. On the Effectiveness of Speculative and Selective Memory Fences. In Proceedings of the International Parallel and Distributed Processing Symposium Symposium, Apr. 2006.
32. C. von Praun, H. W. Cain, J.-D. Choi, and K. D. Ryu. Conditional Memory Ordering. In Proceedings of the 33rd Annual International Symposium on Computer Architecture, pages 41-52, June 2006.
33. T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. Mechanisms for Store-wait-free Multiprocessors. In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007.
34. T. F. Wenisch, R. E. Wunderlich, M. Ferdman, A. Ailamaki, B. Falsafi, and J. C. Hoe. SimFlex: Statistical Sampling of Computer System Simulation. IEEE Micro, 26(4):18-31, 2006.
35. K. C. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2):28-40, Apr. 1996.