Speculative synchronization: Applying thread-level speculation to explicitly parallel applications

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2002, Pages 18-29

  Martínez, José F ^a   Torrellas, Josep ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; EVALUATION; INTERFACES (COMPUTER); PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); SYNCHRONIZATION; COMPUTER OPERATING SYSTEMS; LINGUISTICS; LOCKS (FASTENERS); PARALLEL ARCHITECTURES; PHILOSOPHICAL ASPECTS;

SPECULATIVE SYNCHRONIZATION; THREAD LEVEL SPECULATION;

PARALLEL PROCESSING SYSTEMS; SYNCHRONIZATION;

ACTIVE BARRIER; BUFFER OVERFLOWS; ON THE FLIES; PARALLEL APPLICATION; PARALLEL PROGRAM; PARALLELIZING COMPILER; PROGRAM EXECUTION; RUNTIMES; SYNCHRONIZATION POINTS; THREAD LEVEL SPECULATION;

EID: 0036949529     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (35)

1. S. V. Adve and M. D. Hill. A unified formalization of four shared-memory models. IEEE Transactions on Parallel and Distributed Systems, 4(6):613-624, June 1993.
2. W. Blume, R. Doallo, R. Eigenmann, J. Grout, J. Hoeflinger, T. Lawrence, J. Lee, D. Padua, Y. Paek, B. Pottenger, L. Rauchwerger, and P. Tu, Advanced program restructuring for high-performance computers with Polaris. IEEE Computer, 29(12):78-82, Dec. 1996.
3. M. C. Carlisle and A. Rogers. Software caching and computation migration in Olden. In Symposium on Principles and Practice of Parallel Programming, pages 29-38, Santa Barbara, CA, July 1995.
4. M. Cintra, J. F. Martínez, and J. Torrellas. Architectural support for scalable speculative parallelization in shared-memory multiprocessors. In International Symposium on Computer Architecture, pages 13-24, Vancouver, Canada, June 2000.
5. L. Dagum and R. Menon. OpenMP: An industry-standard API for shared-memory programming. IEEE Computational Science and Engineering, 5(1):46-55, Jan.-Mar. 1998.
6. J. Edler, J. Lipkis, and E. Schonberg. Process management for highly parallel UNIX systems. In USENIX Workshop on Unix and Supercomputers, San Francisco, CA, Sept. 1988.
7. K. Gharachorloo and P. B. Gibbons. Detecting violations of sequential consistency. In Symposium on Parallel Algorithms and Architectures, pages 316-326, Hilton Head, SC, July 1991.
8. K. Gharachorloo, A. Gupta, and J. Hennessy. Two techniques to enhance the performance of memory consistency models. In International Conference on Parallel Processing, pages 1355-1364, St. Charles, IL, Aug. 1991.
9. C. Gniady, B. Falsafi, and T. N. Vijaykumar, Is SC+ILP=RC? In International Symposium on Computer Architecture, pages 162-171, Atlanta, GA, May 1999.
10. S. Gopal, T. N. Vijaykumar, J. E. Smith, and G. S. Sohi. Speculative versioning cache. In International Symposium on High-Performance Computer Architecture, pages 195-205, Las Vegas, NV, Jan.-Feb. 1998.
11. R. Gupta. The Fuzzy Barrier: A mechanism for high-speed synchronization of processors. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 54-63, Boston, MA, Apr. 1989.
12. L. Hammond, M. Wiley, and K. Olukotun. Data speculation support for a chip multiprocessor. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 58-69, San Jose, CA, Oct. 1998.
13. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, second edition, 1996.
14. M. Herlihy. Apologizing versus asking permission: Optimistic concurrency control for abstract data types. ACM Transactions on Database Systems, 15(1): 96-124, Mar. 1990.
15. M. Herlihy. A methodology for implementing highly concurrent data objects. ACM Transactions on Parallel Languages and Systems, 15(5):745-770, Nov. 1993.
16. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural support for lock-free data structures. In International Symposium on Computer Architecture, pages 289-300, San Diego, CA, May 1993.
17. L. I. Kontothanassis, R. W. Wisniewski, and M. L. Scott. Schedule-conscious synchronization. ACM Transactions on Computer Systems, 15 (1):3-40, Feb. 1997.
18. V. Krishnan and J. Torrellas. A direct-execution framework for fast and accurate simulation of superscalar processors. In International Conference on Parallel Architectures and Compilation Techniques, pages 286-293, Paris, France, Oct. 1998.
19. V. Krishnan and J. Torrellas. A chip-multiprocessor architecture with speculative multithreading. IEEE Transactions on Computers, 48(9):866-880, Sept. 1999.
20. H. T. Kung and J. T. Robinson. On optimistic methods for concurrency control. ACM Transactions on Database Systems, 6(2):213-226, June 1981.
21. D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The directory-based cache coherence protocol for the DASH multiprocessor. In International Symposium on Computer Architecture, pages 148-159, Seattle, WA, May 1990.
22. E. Lusk, R. Overbeek, et al. Portable Programs for Parallel Processors. Holt, Rinehart, and Winston, Inc., New York, NY, 1996.
23. P. Marcuello and A. González. Clustered speculative multithreaded processors. In International Conference on Supercomputing, pages 365-372, Rhodes, Greece, June 1999.
24. B. D. Marsh, M. L. Scott, T. J. LeBlanc, and E. P. Markatos. Firstclass user-level threads. In Symposium on Operating System Principles, pages 110-121, Pacific Grove, CA, Oct. 1991.
25. J. F. Martinez and J. Torrellas. Speculative Locks for concurrent execution of critical sections in shared-memory multiprocessors. In Workshop on Memory Performance Issues, Gothenburg, Sweden, June 2001.
26. V. S. Pai, P. Ranganathan, S. V. Adve, and T. Harton. An evaluation of memory consistency models for shared-memory systems with ILP processors. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 12-23, Cambridge, MA, Oct. 1996.
27. R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling highly concurrent multithreaded execution. In International Symposium on Microarchitecture, pages 294-305, Austin, TX, Dec. 2001.
28. R. Rajwar and J. R. Goodman. Transactional lock-free execution of lock-based codes. In International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, Oct. 2002.
29. M. C. Rinard. Effective fine-grain synchronization for automatically parallelized programs using optimistic synchronization. ACM Transactions on Computer Systems, 17(4):337-371, Nov. 1999.
30. T. Sato, K. Ohno, and H. Nakashima. A mechanism for speculative memory accesses following synchronizing operations. In International Parallel and Distributed Processing Symposium, pages 145-154, Cancun, Mexico, May 2000.
31. J. G. Steffan, C. B. Colohan, A. Zhai, and T. C. Mowry. A scalable approach to thread-level speculation. In International Symposium on Computer Architecture, pages 1-12, Vancouver, Canada, June 2000.
32. J. M. Stone, H. S. Stone, P. Heidelberg and J. Turek. Multiple reservations and the Oklahoma Update. IEEE Parallel and Distributed Technology, 1(4):58-71, Nov. 1993.
33. D. L. Weaver and T. Germond, editors. The SPARC Architecture Manual. PTR Prentice Hall, 1994.
34. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In International Symposium on Computer Architecture, pages 24-36, Santa Margherita Ligure, Italy, June 1995.
35. K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro. 6(2):28-40, Apr. 1996.