Speculative lock elision: Enabling highly concurrent multithreaded execution

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 2001, Pages 294-305

  Rajwar, Ravi ^a   Goodman, James R ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; MULTIPROCESSING SYSTEMS; SERVERS; SYNCHRONIZATION;

SPECULATIVE LOCK ELISION (SLE);

CONCURRENCY CONTROL;

EID: 0035694494     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (40)

1. Performance issues in non-blocking synchronization on shared-memory multiprocessors
2. Piranha: A scalable architecture based on single-chip multiprocessing
3. Practical considerations for lock-free concurrent objects
4. Shoring up persistent applications
5. Giga-plane-XB: Extending the ultra enterprise family
6. A study of common pitfalls in simple multi-threaded programs
7. A hardware mechanism for dynamic reordering of memory references
8. Two techniques to enhance the performance of memory consistency models
9. Is SC + ILP = RC?
10. Speculative versioning cache
11. A methodology for implementing highly concurrent data objects
12. Transactional memory: Architectural support for lock-free data structures
13. Multiprocessors should support simple memory consistency models
14. A new approach to exclusive data access in shared memory multiprocessors
15. Efficient synchronization: Let them eat QOLB
16. A dual-CPU processor chip
17. Performance analysis using very large memory on the 64-bit alphaserver system
18. On optimistic methods of concurrency control
19. Concurrent reading and writing
20. The SGI origin: A ccNUMA highly scalable server
21. Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories
22. On the value locality of store instructions
23. Less optimism about optimistic concurrency control
24. ARIES: A transaction recovery method supporting fine-granularity locking and partial rollbacks using write-ahead logging
25. Improving the throughput of synchronization by insertion of delays
26. Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models
27. Dynamic decentralized cache schemes for MIMD parallel processors
28. SPLASH: Stanford parallel applications for shared memory
29. Implementation of precise interrupts in pipelined processors
30. Multiple reservations and the oklahoma update
31. A multi-threaded 64-bit PowerPC commercial RISC processor design
32. Concurrency control: Methods, performance, and analysis
33. The SPLASH-2 programs: Characterization and methodological considerations