Hardware atomicity for reliable software speculation

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 174-185

  Neelakantam, Naveen ^a,b   Rajwar, Ravi ^b   Srinivas, Suresh ^b   Srinivasan, Uma ^b   Zilles, Craig ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Atomicity; Checkpoint; Isolation; Java; Optimization; Speculation

Indexed keywords

ATOMICITY; CHECKPOINT; DYNAMIC INSTRUCTION;

COMPUTATIONAL COMPLEXITY; COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; OPTIMIZATION;

PROGRAM COMPILERS;

EID: 35348918162     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250684     Document Type: Conference Paper

References (23)

1. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2003.
2. S. M. Blackburn et al. The DaCapo Benchmarks: Java Benchmarking Development and Analysis. In Proceedings of the 21st annual ACM SIGPLAN conference on Object-Oriented Programing, Systems, Languages, and Applications, Oct. 2006.
3. Y. Chou, L. Spracklen, and S. G. Abraham. Store Memory-Level Parallelism Optimizations for Commercial Applications. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2005.
4. A. Cristal et al. Out-of-Order Commit Processors. In Proceedings of the Ninth IEEE Symposium on High-Performance Computer Architecture, Feb. 2003.
5. P. Damron et al. Hybrid Transactional Memory. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2006.
6. J. C. Dehnert et al. The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-life Challenges. In Proceedings of the International Symposium on Code Generation and Optimization, 2003.
7. B. Fahs et al. Performance Characterization of a Hardware Framework for Dynamic Optimization. In Proceedings of the 34th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2001.
8. G. Hamerly et al. SimPoint 3.0: Faster and More Flexible Program Analysis. Journal of Instruction Level Parallelism, 1, Sept 2005.
9. Harmony Dynamic Runtime Layer Virtual Machine (DRLVM). http://harmony.apache.org/subcomponents/drlvm.
10. W. M. Hwu et al. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. Journal of Supercomputing, 7(1):229-248, Mar 1993.
11. K. Kawachiya, A. Koseki, and T. Onodera. Lock Reservation: Java locks can mostly do without atomic operations. In Proceedings of the 17th annual ACM SIGPLAN conference on Object-Oriented Programing, Systems, Languages, and Applications, 2002.
12. J. R. Larus and R. Rajwar. Transactional Memory. Morgan and Claypool, Dec. 2006.
13. L. ling Chen and Y. Wu. Fast Forward: Aggressive Compiler Optimization with Speculative Multi-Threaded Support. In Workshop on Multithreaded Execution, Architecture and Compilation, 2000.
14. J. F. Martinez et al. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2002.
15. R. Muth and S. Debray. Partial Inlining. Technical report, Univ. of Arizona, Dept. of Computer Science, 1997.
16. S. J. Patel and S. S. Lumetta. rePLay: A Hardware Framework for Dynamic Optimization. IEEE Transactions on Computers, 50(6):590-608, 2001.
17. E. Perelman et al. Cross Binary Simulation Points. In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software, Apr. 2007.
18. R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Proceedings of the 34th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2001.
19. M. Smith. Overcoming the Challenges of Feedback-Directged Optiization. In Proc. Proc. ACM SIGPLAN Workshop on Dynamic and Adaptive Compilation and Optimization, Jan. 2000.
20. K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Slipstream Processors: Improving both Performance and Fault Tolerance. In Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, Nov. 2000.
21. W. A. Wulf. Compilers and Computer Architecture. IEEE Computer, 14(7):41-47, 1981.
22. C. Zilles and N. Neelakantam. Reactive Techniques for Controlling Software Speculation. In Proceedings of the International Symposium on Code Generation and Optimization, 2005.
23. C. Zilles and G. Sohi. Master/Slave Speculative Parallelization. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2002.