Tradeoffs in buffering memory state for thread-level speculation in multiprocessors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 191-202

  Garzaran, M J ^a   Prvulovic, M ^b   Llaberia, J M ^c   Vinals, V ^a   Rauchwerger, L ^d   Torrellas, J ^b  

^a UNIVERSITY OF ZARAGOZA   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^d TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Memory management; Merging; Pollution; Proposals; Taxonomy

Indexed keywords

COMPUTER ARCHITECTURE; MEMORY ARCHITECTURE; MERGING; MULTIPROCESSING SYSTEMS; POLLUTION; SUPERCOMPUTERS; TAXONOMIES;

ARCHITECTURAL FRAMEWORKS; ARCHITECTURAL SUPPORT; DISTRIBUTED CACHE; MEMORY MANAGEMENT; NUMERICAL APPLICATIONS; PROPOSALS; THREAD LEVEL SPECULATION; TRADE-OFF ANALYSIS;

CACHE MEMORY;

EID: 43949089615     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183537     Document Type: Conference Paper

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