Programming with transactional coherence and consistency (TCC)

11th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XI

Volumn , Issue , 2004, Pages 1-13

  Hammond, Lance ^a   Carlstrom, Brian D ^a   Wong, Vicky ^a   Hertzberg, Ben ^a   Chen, Mike ^a   Kozyrakis, Christos ^a   Olukotun, Kunle ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Feedback optimization; Multiprocessor architecture; Transactions

Indexed keywords

CODES (SYMBOLS); COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; CONCURRENT ENGINEERING; FEEDBACK; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

FEEDBACK OPTIMIZATION; MULTIPROCESSOR ARCHITECTURE; TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC); TRANSACTIONS;

COMPUTER PROGRAMMING;

EID: 12844266720     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1024393.1024395     Document Type: Conference Paper

References (38)

1. S.V. Adve and K. Gharachorloo, "Shared Memory Consistency Models: A Tutorial," IEEE Computer, Vol. 29 No. 12, pp. 66-76, December 1996.
2. th Intl. Symposium on Computer Architecture, pp. 248-259, Vancouver, Canada, June 2000.
3. K. Arnold, J. Gosling, and D. Holmes, The Java Programming Language, Third Edition, Addison-Wesley Professional, 2000.
4. th International Parallel Processing Symposium, Geneva, Switzerland, 1997.
5. Broadcom Corp., "The Broadcom BCM-1250 Multiprocessor," Presentation at 2002 Embedded Processor Forum, April 2002.
6. Byte Magazine, jBYTEmark Benchmark, http://www.byte.com, CMP Media LLC, 1999.
7. th International Symposium on Computer Architecture (ISCA-30), pp. 434-445, June 2003.
8. M. Dubois, et. al., "Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs," Proceedings of Supercomputing '91, November 1991.
9. J. Gray and A. Reuter, Transaction Processing: Concepts and Techniques, Morgan Kaufmann, 1993.
10. W. Gropp, E. Lusk, and A. Skjellum, Using MPI: Portable Parallel Programming with the Message Passing Interface, MIT Press, 1994.
11. L. Hammond, B. Hubbert, M. Siu, M. Prabhu, M. Chen, and K. Olukotun, "The Stanford Hydra CMP," IEEE MICRO Magazine, pp. 71-84, March-April 2000.
12. st Annual Symposium on Computer Architecture (ISCA-31), pp. 102-113, June 2004.
13. th ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA-2003), October 2003.
14. nd Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), July 2003.
15. th International Symposium on Computer Architecture (ISCA-20), pp. 289-300, 1993.
16. IBM Corporation, Encina Transactional-C Programmer's Guide and Reference for AK, SC23-2465-02, 1994.
17. Java Grande Forum, Java Grande Benchmark Suite, http://www.epcc.ed.ac.uk/ javagrande/, 2000.
18. R. Kalla, B. Sinharoy, and J. Tendler, "Simultaneous Multithreading Implementation in POWERS," Conference Record of Hot Chips 15 Symposium, Palo Alto, CA, August 2003.
19. P. Keleher, A. L. Cox, and W. Zwaenepoel, "Lazy Release Consistency for Software Distributed Shared Memory," Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, pp. 279-283, Orlando, PL, 1999.
20. T. Knight, "An Architecture for Mostly Functional Languages," Proceedings of the 1986 ACM Conference on Lisp and Functional Programming, August 1986.
21. L. I. Kontothanassis, M. L. Scott, and R. Bianchini, "Lazy Release Consistency for Hardware-Coherent Multiprocessors," Proceedings of Supercomputing '95, San Diego, CA, Dec. 1995.
22. V. Krishnan and J. Torrellas, "A Chip Multiprocessor Architecture with Speculative Multithreading," IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, Vol. 48 No. 9, pp. 866-880, September 1999.
23. H. T. Kung and J. T. Robinson, "On Optimistic Methods for Concurrency Control," ACM Transactions on Database Systems, Vol. 6 No. 2, June 1981.
24. th Annual International Symposium on Microarchitecture (MICRO-97), Research Triangle Park, NC, December 1997.
25. B. Lewis and D.J. Berg, Multithreaded Programming with Pthreads, Prentice Hall, 1998.
26. th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), pp. 18-29, October 2002.
27. K. Olukotun, L. Hammond, and M. Willey, "Improving the Performance of Speculatively Parallel Applications on the Hydra CMP," Proceedings of the 1999 ACM International Conference on Supercomputing (ICS-99), pp. 21-30, Rhodes, Greece, June 1999.
28. th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), pp. 184-196, October 2002.
29. M. K. Prabhu and K. Olukotun, "Using Thread-Level Speculation to Simplify Manual Parallelization," Proceedings of the Principles and Practice of Parallel Programming (PPoPP), pp. 1-12, June 2003.
30. th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), pp. 5-17, October 2002.
31. R. Raman, "UltraSparc Gemini: Dual CPU Processor," Conference Record of Hot Chips 15 Symposium, Palo Alto, CA, August 2003.
32. th Annual ACM Symposium on Principles of Distributed Computing, pp. 204-213, Ottawa, Canada, August 20-23, 1995.
33. nd Annual International Symposium on Computer Architecture, pp. 414-425, Santa Margherita Ligure, Italy, June 1995.
34. Standard Performance Evaluation Corporation, SPECjbb2000 v1.01, http://www.spec.org/jbb2000/, Warrenton, VA, 2000.
35. Standard Performance Evaluation Corporation, SPEC*, http://www.specbench.org/, Warrenton, VA, 1995-2000.
36. J. Steffan and T. Mowry, "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization," Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, pp. 2-13, Las Vegas, Nevada, 1998.
37. st International Symposium on Microarchitecture (MICRO-31), pp. 81-92, December 1998.
38. T. Wilkinson, Kaffe Virtual Machine, http://kaffe.org, 1997-2002.