On-chip process variation detection and compensation using delay and slew-rate monitoring circuits

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 815-820

  Ghosh, Amlan ^a   Rao, Rahul M ^b   Chuang, Ching Te ^b   Brown, Richard B ^a  

^a UNIVERSITY OF UTAH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BODY-BIASING; COMPENSATION SCHEMES; CRITICAL PATH DELAYS; DELAY METRICS; DESIGN CONSIDERATIONS; ELECTRONIC DESIGNS; INTERNATIONAL SYMPOSIUM; ON CHIPS; PARAMETRIC YIELD; PMOS DEVICES; POST-FABRICATION; POWER-PERFORMANCE; PROCESS VARIATIONS; SIMULATION RESULTS; SLEW RATES; SOI TECHNOLOGY; TOTAL POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRONICS ENGINEERING; OPTICAL DESIGN;

PROCESS ENGINEERING;

EID: 49849087939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479843     Document Type: Conference Paper

References (12)

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