Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 9-12

  Tschanz, James ^a   Narendra, Siva ^a   Keshavarzi, Ali ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE POWER; ADAPTIVE BODY BIAS; ADAPTIVE CIRCUIT; ADAPTIVE SUPPLY VOLTAGE; LEAKAGE DISTRIBUTION; LEAKAGE POWER; PARAMETER VARIATION; TEST-CHIP;

MICROPROCESSOR CHIPS;

EID: 39749185147     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464511     Document Type: Conference Paper

References (5)

1. K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration", IEEE J. Solid-State Circuits, vol. 37, pp. 183-190, Feb. 2002.
2. M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, "A 1000-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias", in IEEE ISSCC Dig. Tech. Papers, 2000, pp. 420-421.
3. J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage", in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 422-423.
4. A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, "Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs", in Proc. ISLPED, Aug. 2001, pp. 207-212.
5. S. Narendra, M. Haycock, V. Govindarajulu, V. Erraguntla, H. Wilson, S. Vangal, A. Pangal, E. Seligman, R. Nair, A. Keshavarzi, B. Bloechel, G. Dermer, R. Mooney, N. Borkar, S. Borkar, and V. De, "1.1V 1 GHz communications router with on-chip body bias in 150 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp.270-271.