Overview of 3D Integration Process Technology

Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits

Volumn 1, Issue , 2008, Pages 25-44

  Garrou, Philip ^a   Bower, Christopher ^b  

^a Microelectronic Consultants of North Carolina   (United States)

^b SEMPRIUS INC   (United States)

Author keywords

Back end of line (BEOL); Deep reactive ion etching (DRIE); Front end of line (FEOL); Handle wafer; Vias first; Vias last

Indexed keywords

EID: 70449601403     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9783527623051.ch3     Document Type: Chapter

References (32)

1. Roozeboom, F. et al. (2006) Passive and heterogeneous integration towards a Si based system in package concept. Thin Solid Films, 504, 391.
2. Henry, D., Baillin, X., Lapras, V., Vaudaine, M.H. et al. (2007) Via first technology development based on high aspect ratio trenches filled with doped polysilicon. 57th ECTC, Reno, Nevada, p. 830.
3. Mitsuhashi, T. et al. (2007) Development of 3D processing process technology for stacked memory. MRS Symposium Proceedings, Enabling Technologies for 3D Integration (eds C. Bower, P.Garrou, P. Ramm and K. Takahashi), 970, p. 155.
4. Koyanagi, M. et al. (2006) 3D integration technology based on wafer bonding with vertical buried interconnect. IEEE Transactions on Electron Devices, 53, 2799.
5. Takahashi, K., Taguchi, Y., Tomisaka, M. et al. (2004) Process integration of 3D chip stack with vertical interconnection, Proceedings of the 54th Electronic Components and Technology Conference (ECTC 2004), Las Vegas, NV, p. 601-609.
6. Garrou, P. (Oct 2006) 3D Integration moving forward. Semiconductor International, p. SP 12.
7. Toftness, R., Boyle, A. and Gillen, D. (2005) Laser technology for wafer dicing and microvia drilling for next generation wafers. Proceedings SPIE, 5713, 54.
8. Rodin, A. (2007) High Throughput Laser Via and Dicing Process. Proceed. Peaks in Packaging, Whitefish MT.
9. Chin, B. and Van de Ven, E. (1988) Plasma TEOS for interlayer dielectric applications. Solid State Technology, 31, 119.
10. Cote, D. et al. (1999) Plasma assisted CVD of dielectric thin films for ULSI semiconductor circuits. IBM Journal of Research, 43, p. 5-38.
11. Garrou, P. et al. (1997) Polymers in packaging. in Microelectronics Packaging Handbook (eds Tummala, Rymaszewski and Klopfenstein), Chapman & Hall, New York.
12. Gobert, J. et al. (1997) IC compatible fabrication of through-wafer conductive vias. Proceedings SPIE, 3223, 17.
13. Sabuncuoglu, D., Pham, N.,Majeed, B. et al. (2007) Sloped through wafer vias for 3D wafer level packaging, Proceedings of the 57th Electronic Components and Technology Conference (ECTC, 2007), Reno, NV, p. 643.
14. Jang, D.M. et al. (2007) Development and Evaluation of 3D SiP with Vertically Interconnected TSV, Proceedings of the 57th Electronic Components and Technology Conference (ECTC 2007), Reno, NV, p. 847.
15. Ogawa, E., Lee, K., Blaschke, V. and Ho, P. (2002) Electromigration reliability issues in dual damascene Cu interconnections. IEEE Transactions on Reliability, 51, 403.
16. Hashim, I., Pavate, V., Ding, P. et al. IMP Ta/Cu Seed Layer Technology for High Aspect Ratio Via Fill. Proc. SPIE-Int. Soc. Opt. Eng., Volume 3508, Multilevel Interconnect Technology II, (eds M. Graf, D. Patel, and Klopfenstein).
17. Cho, B. and Lee, W. (2007) Filling of very fine via holes for 3D SiP by using ionized metal plasma sputtering and electroplating. International Conference Electronic Packaging, Tokyo, Japan.
18. Jang, D.M. et al. (2007) Development and Evaluation of 3D SiP with Vertically Interconnected TSV, ECTC, 847.
19. Ko, Y., Seo, B.,Park, D. et al. (2002) Additive vapor effect on the conformal coverage of a high aspect ratio trench using MOCVD copper metallization. Semiconductor Science and Technology, 17, 978.
20. Koide, T. and Sekiguchi, A. (2003) Formation of copper feed-through electrodes using CVD. Proceedings MES, 404.
21. Zhang, M. et al. (1999) Optimization of copper CVD film properties using precursor of Cu(hfac)(tmvs) with variations of additive content. Proceedings IITC, 170.
22. Kenny, S. and Matejat, K. (Feb. 21 2001) HDI production using pulse plating with insoluble anodes. Circui Tree.
23. Siniaguine, O. (1998) Atmospheric downstream plasma etching of Si wafers. Proceedings International Elect. Manuf. Tech. Symposium, p. 139.
24. Hendrix, M., Drews, S. and Hurd, T. (2000) Advances of wet chemical spin processing for wafer thinning and packaging applications. Proceed. International Elect. Manuf. Tech. Symp., p. 229.
25. Pinel, S., Lepinos, F., Cazarre, A. et al. (2002) Impact of ultra-thinning on DC characteristics of MOSFET devices. European Physical Journal, 17, 41.
26. Takahashi, S., Hayashi, Y., Kunio, T. and Endo, N. (1992) Characteristics of thin film devices for a stacked-type MCM. IEEE Multi Chip Module Conference, p. 159.
27. Ramm, P. (Oct 2004) Vertical system integration technologies. Adv. Metals Conference Workshop on 3D Integration of Semiconductor Devices.
28. Pasquariello, D. (2001) Plasma assisted low temperature semiconductor wafer bonding, Dissertation, Uppsala University, Sweden.
29. Zucker, O., Langheinrich, W. and Kulozik, M. (1993) Application of oxygen plasma processing to silicon direct bonding. Sensors & Actuators A, 6, 227.
30. Kurahashi, T., Onada, M. and Hatton, T. (1991) Sensors utilizing Si wafer direct bonding at low temperature. Proceed. 2nd International Symp Micro Machine and Human Science, Nagoya, p. 173.
31. Rief, R., Tan, C.S., Fan, A. et al. (April 2004) Technology and applications of 3D integration enabled by bonding. 3D Architectures for 3D Semiconductor Integration and Packaging Conference, Burlingame CA.
32. Niklaus, F., Enoksson, P., Kalvesten, E. and Stemme, G. (2003) A method to maintain wafer bonding alignment precision during adhesive wafer bonding. Sensors & Actuators A, 107, 273.