Advantages of wet chemical spin-processing for wafer thinning and packaging applications

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2000, Pages 229-236

  Hendrix, Mark ^a   Drews, Scott ^a   Hurd, Trace ^b  

^a STMICROELECTRONICS   (Italy)

^b SEZ America Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; FINISHING; SILICON WAFERS; STRESS RELIEF; SURFACE ROUGHNESS;

WAFER THINNING; WET CHEMICAL SPIN PROCESSING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034448409     PISSN: 10898190     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEMT.2000.910733     Document Type: Article

References (2)