-
1
-
-
84949189232
-
-
Vassiliadis, S., Wong, S., Cotofana, S.D.: The MOLEN μρ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, 2147, pp. 275-285. Springer, Heidelberg (2001)
-
Vassiliadis, S., Wong, S., Cotofana, S.D.: The MOLEN μρ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275-285. Springer, Heidelberg (2001)
-
-
-
-
2
-
-
70350388184
-
-
Heysters, P.M.: Coarse-grained reconfigurable computing for power aware applications. In: ERSA, pp. 272-280 (2006)
-
Heysters, P.M.: Coarse-grained reconfigurable computing for power aware applications. In: ERSA, pp. 272-280 (2006)
-
-
-
-
3
-
-
70350403290
-
-
Seno, K., Yamazaki, M.: Virtual mobile engine (VME) LSI that 'changes its spots' achievies ultralow power and diverse functionality. CX-News 42 (2005), http://www.sony.com
-
Seno, K., Yamazaki, M.: Virtual mobile engine (VME) LSI that 'changes its spots' achievies ultralow power and diverse functionality. CX-News 42 (2005), http://www.sony.com
-
-
-
-
4
-
-
2042458649
-
A survey of processors with expliclicit multithreading
-
Ungerer, T., Robic, B., Silc, J.: A survey of processors with expliclicit multithreading. ACM Computing Surveys 35(1), 29-63 (2003)
-
(2003)
ACM Computing Surveys
, vol.35
, Issue.1
, pp. 29-63
-
-
Ungerer, T.1
Robic, B.2
Silc, J.3
-
5
-
-
79955133514
-
-
Sima, M., Vassiliadis, S., Cotofana, S.D., van Eijndhoven, J.T.J., Vissers, K.A.: Field-programmable custom computing machines - a taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, 2438, pp. 79-88. Springer, Heidelberg (2002)
-
Sima, M., Vassiliadis, S., Cotofana, S.D., van Eijndhoven, J.T.J., Vissers, K.A.: Field-programmable custom computing machines - a taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 79-88. Springer, Heidelberg (2002)
-
-
-
-
6
-
-
70350361735
-
The first real operating system for reconfigurable computers. In: ACSAC
-
Los Alamitos
-
Wigley, G.B., Kearney, D.A.: The first real operating system for reconfigurable computers. In: ACSAC, pp. 129-136. IEEE Computer Society Press, Los Alamitos (2000)
-
(2000)
IEEE Computer Society Press
, pp. 129-136
-
-
Wigley, G.B.1
Kearney, D.A.2
-
7
-
-
34548058625
-
-
Wu, K., Kanstein, A., Madsen, J., Berekovic, M.: MT-ADRES: Multithreading on coarse-grained reconfigurable architecture. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, 4419, pp. 26-38. Springer, Heidelberg (2007)
-
Wu, K., Kanstein, A., Madsen, J., Berekovic, M.: MT-ADRES: Multithreading on coarse-grained reconfigurable architecture. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds.) ARCS 2007. LNCS, vol. 4419, pp. 26-38. Springer, Heidelberg (2007)
-
-
-
-
8
-
-
70350360800
-
-
Mamidi, S., Schulte, M., Iancu, D., Glossner, J.: Architecture support for reconfigurable multithreaded processors in programmable communication systems. In: ASAP, pp. 320-327. IEEE Press, Los Alamitos (2007)
-
Mamidi, S., Schulte, M., Iancu, D., Glossner, J.: Architecture support for reconfigurable multithreaded processors in programmable communication systems. In: ASAP, pp. 320-327. IEEE Press, Los Alamitos (2007)
-
-
-
-
9
-
-
70350369409
-
-
Uhrig, S., Maier, S., Kuzmanov, G.K., Ungerer, T.: Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In: RAW, pp. 209-217 (2006)
-
Uhrig, S., Maier, S., Kuzmanov, G.K., Ungerer, T.: Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In: RAW, pp. 209-217 (2006)
-
-
-
-
10
-
-
46249084693
-
-
FPL, pp
-
Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., Andrews, D.: HTHREADS: a computational model for reconfigurable devices. In: FPL, pp. 885-888 (2006)
-
(2006)
HTHREADS: A computational model for reconfigurable devices
, pp. 885-888
-
-
Peck, W.1
Anderson, E.2
Agron, J.3
Stevens, J.4
Baijot, F.5
Andrews, D.6
-
11
-
-
0000227930
-
Reconfigurable computing: A survey of systems and software
-
Compton, K., Hauck, S.: Reconfigurable computing: a survey of systems and software. ACM Computing Surveys 34(2), 171-210 (2002)
-
(2002)
ACM Computing Surveys
, vol.34
, Issue.2
, pp. 171-210
-
-
Compton, K.1
Hauck, S.2
-
12
-
-
70350368877
-
-
Diessel, O., Wigley, G.B.: Opportunities for operating systems research in reconfigurable computing. In: ACRC (1999)
-
Diessel, O., Wigley, G.B.: Opportunities for operating systems research in reconfigurable computing. In: ACRC (1999)
-
-
-
-
13
-
-
40549129379
-
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
-
So, H.K.-H., Brodersen, R.: A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Transactions on Embedded Computing Systems 7(2), 1401-1407 (2008)
-
(2008)
ACM Transactions on Embedded Computing Systems
, vol.7
, Issue.2
, pp. 1401-1407
-
-
So, H.K.-H.1
Brodersen, R.2
-
14
-
-
70350368875
-
-
Zhou, B., Qui, W., Peng, C.-L.: An operating system framework for reconfigurable systems. In: CIT, pp. 781-787 (2005)
-
Zhou, B., Qui, W., Peng, C.-L.: An operating system framework for reconfigurable systems. In: CIT, pp. 781-787 (2005)
-
-
-
-
15
-
-
33749549866
-
Multitasking on reconfigurable architectures: Microarchitecture support and dynamic scheduling
-
Noguera, J., Badia, R.M.: Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. Trans. on Embedded Computing Sys. 3(2), 385-406 (2004)
-
(2004)
Trans. on Embedded Computing Sys
, vol.3
, Issue.2
, pp. 385-406
-
-
Noguera, J.1
Badia, R.M.2
-
16
-
-
9544245821
-
Run-time support for heterogeneous multitasking on reconfigurable SoCs
-
Marescaux, T., Nollet, V., Mignolet, J.-Y., Bartic, A., Moffat, W., Avasare, P., Coene, P., Verkest, D., Vernalde, S., Lauwereins, R.: Run-time support for heterogeneous multitasking on reconfigurable SoCs. Integration 38(1), 107-130 (2004)
-
(2004)
Integration
, vol.38
, Issue.1
, pp. 107-130
-
-
Marescaux, T.1
Nollet, V.2
Mignolet, J.-Y.3
Bartic, A.4
Moffat, W.5
Avasare, P.6
Coene, P.7
Verkest, D.8
Vernalde, S.9
Lauwereins, R.10
-
17
-
-
70350356035
-
State-of-the-art reconfigurable multithreading architectures
-
Technical Report, CE-TR-2009-02
-
Zaykov, P.G., Kuzmanov, G.K., Gaydadjiev, G.N.: State-of-the-art reconfigurable multithreading architectures. Technical Report - CE-TR-2009-02 (2009)
-
(2009)
-
-
Zaykov, P.G.1
Kuzmanov, G.K.2
Gaydadjiev, G.N.3
-
18
-
-
70350360917
-
-
The convey HC-1 computer, architecture overview (white paper), p. 11 (2008), http://www.conveycomputer.com
-
The convey HC-1 computer, architecture overview (white paper), p. 11 (2008), http://www.conveycomputer.com
-
-
-
-
19
-
-
70350420453
-
-
Gibeling, G., Schultz, A., Asanovic, K.: The RAMP architecture & description language. In: WARFP (2006)
-
Gibeling, G., Schultz, A., Asanovic, K.: The RAMP architecture & description language. In: WARFP (2006)
-
-
-
-
20
-
-
79955152352
-
-
Haynes, S.D., Epsom, H.G., Cooper, R.J., McAlpine, P.L.: UltraSONIC: A reconfigurable architecture for video image processing. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, 2438, pp. 482-491. Springer, Heidelberg (2002)
-
Haynes, S.D., Epsom, H.G., Cooper, R.J., McAlpine, P.L.: UltraSONIC: A reconfigurable architecture for video image processing. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 482-491. Springer, Heidelberg (2002)
-
-
-
-
21
-
-
48149083972
-
-
Satrawala, A., Varadarajan, K., Lie, M., Nandy, S., Narayan, R.: Redefine: Architecture of a soc fabric for runtime composition of computation structures. In: FPL 2007, pp. 558-561 (2007)
-
Satrawala, A., Varadarajan, K., Lie, M., Nandy, S., Narayan, R.: Redefine: Architecture of a soc fabric for runtime composition of computation structures. In: FPL 2007, pp. 558-561 (2007)
-
-
-
-
22
-
-
35248899829
-
-
Wallner, S.: A reconfigurable multi-threaded architecture model. In: Omondi, A.R., Sedukhin, S.G. (eds.) ACSAC 2003. LNCS, 2823, pp. 193-207. Springer, Heidelberg (2003)
-
Wallner, S.: A reconfigurable multi-threaded architecture model. In: Omondi, A.R., Sedukhin, S.G. (eds.) ACSAC 2003. LNCS, vol. 2823, pp. 193-207. Springer, Heidelberg (2003)
-
-
-
-
23
-
-
49749147472
-
-
Bauer, L., Shafique, M., Kreutz, S., Henkel, J.: Run-time system for an extensible embedded processor with dynamic instruction set. In: DATE, pp. 752-757 (2008)
-
Bauer, L., Shafique, M., Kreutz, S., Henkel, J.: Run-time system for an extensible embedded processor with dynamic instruction set. In: DATE, pp. 752-757 (2008)
-
-
-
-
24
-
-
33646423341
-
-
FPL, pp
-
Steiger, C., Walder, H., Platzner, M.: Heuristics for online scheduling real-time tasks to partially reconfigurable devices. In: FPL, pp. 575-584 (2003)
-
(2003)
Heuristics for online scheduling real-time tasks to partially reconfigurable devices
, pp. 575-584
-
-
Steiger, C.1
Walder, H.2
Platzner, M.3
-
25
-
-
38049095519
-
-
Zhou, X., Wang, Y., Huang, X.-Z., Peng, C.-L.: On-line scheduling of real-time tasks for reconfigurable computing system. In: FPT, pp. 57-64 (2006)
-
Zhou, X., Wang, Y., Huang, X.-Z., Peng, C.-L.: On-line scheduling of real-time tasks for reconfigurable computing system. In: FPT, pp. 57-64 (2006)
-
-
-
-
26
-
-
70350403288
-
Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads
-
Miami, Florida
-
Angermeier, J., Teich, J.: Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads. In: Proceedings 15th Reconfigurable Architectures Workshop, Miami, Florida (2008)
-
(2008)
Proceedings 15th Reconfigurable Architectures Workshop
-
-
Angermeier, J.1
Teich, J.2
-
27
-
-
27344460873
-
A reconfiguration manager for dynamically reconfigurable hardware
-
Resano, J., Mozos, D., Verkest, D., Catthoor, F.: A reconfiguration manager for dynamically reconfigurable hardware. IEEE Design & Test of Computers 22(5), 452-460 (2005)
-
(2005)
IEEE Design & Test of Computers
, vol.22
, Issue.5
, pp. 452-460
-
-
Resano, J.1
Mozos, D.2
Verkest, D.3
Catthoor, F.4
-
29
-
-
0036382691
-
-
Li, Z., Hauck, S.: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: FPGA, pp. 187-195 (2002)
-
Li, Z., Hauck, S.: Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In: FPGA, pp. 187-195 (2002)
-
-
-
-
30
-
-
0347566174
-
Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: RTSS
-
Los Alamitos
-
Steiger, C., Walder, H., Platzner, M., Thiele, L.: Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: RTSS, pp. 224-235. IEEE Computer Society, Los Alamitos (2003)
-
(2003)
IEEE Computer Society
, pp. 224-235
-
-
Steiger, C.1
Walder, H.2
Platzner, M.3
Thiele, L.4
-
32
-
-
33746100828
-
-
FPL, pp, IEEE Press, Los Alamitos 2005
-
Kalte, H., Porrmann, M.: Context saving and restoring for multitasking in reconfigurable systems. In: FPL, pp. 223-228. IEEE Press, Los Alamitos (2005)
-
Context saving and restoring for multitasking in reconfigurable systems
, pp. 223-228
-
-
Kalte, H.1
Porrmann, M.2
-
33
-
-
84920348239
-
-
Simmler, H., Levinson, L.: Multitasking on FPGA coprocessors. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, 1896, pp. 121-130. Springer, Heidelberg (2000)
-
Simmler, H., Levinson, L.: Multitasking on FPGA coprocessors. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 121-130. Springer, Heidelberg (2000)
-
-
-
-
34
-
-
34247607804
-
The Erlangen Slot Machine: A dynamically reconfigurable fpga-based computer
-
Majer, M., Teich, J., Ahmadinia, A., Bobda, C.: The Erlangen Slot Machine: A dynamically reconfigurable fpga-based computer. VLSI Signal Processing 47(1), 15-31 (2007)
-
(2007)
VLSI Signal Processing
, vol.47
, Issue.1
, pp. 15-31
-
-
Majer, M.1
Teich, J.2
Ahmadinia, A.3
Bobda, C.4
-
35
-
-
14244263639
-
-
Ahmadinia, A., Bobda, C., Koch, D., Majer, M., Teich, J.: Task scheduling for heterogeneous reconfigurable computers. In: SBCCI, pp. 22-27 (2004)
-
Ahmadinia, A., Bobda, C., Koch, D., Majer, M., Teich, J.: Task scheduling for heterogeneous reconfigurable computers. In: SBCCI, pp. 22-27 (2004)
-
-
-
-
36
-
-
34548722028
-
-
Chen, Y., Chen, S.Y.: Cost-driven hybrid configuration prefetching for partial reconfigurable coprocessor. In: IPDPS, pp. 1-8. IEEE Press, Los Alamitos (2007)
-
Chen, Y., Chen, S.Y.: Cost-driven hybrid configuration prefetching for partial reconfigurable coprocessor. In: IPDPS, pp. 1-8. IEEE Press, Los Alamitos (2007)
-
-
-
-
37
-
-
33644587476
-
Micro-task processing in heterogeneous reconfigurable systems
-
Wallner, S.: Micro-task processing in heterogeneous reconfigurable systems. J. Comput. Sci. Technol. 20(5), 624-634 (2005)
-
(2005)
J. Comput. Sci. Technol
, vol.20
, Issue.5
, pp. 624-634
-
-
Wallner, S.1
|