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Volumn 3, Issue 2, 2004, Pages 385-406

Multitasking on Reconfigurable Architectures: Microarchitecture Support and Dynamic Scheduling

Author keywords

Adaptable architectures and microarchitectures; Algorithms; Design; dynamic scheduling; Performance; runtime support for dynamic reconfiguration

Indexed keywords


EID: 33749549866     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/993396.993404     Document Type: Article
Times cited : (64)

References (28)
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    • Scheduling for embedded real-time systems
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    • Balarin, F. et al. 1998. Scheduling for embedded real-time systems.IEEE Des. Test Comput. 15 (Jan.-Mar.), 1.
    • (1998) IEEE Des. Test Comput. , pp. 1
    • Balarin, F.1
  • 2
    • 0033706197 scopus 로고    scopus 로고
    • A survey of design techniques for system-level dynamic power management
    • Benini, L., Bogliolo, A., Micheli De., G. 2000. A survey of design techniques for system-level dynamic power management.IEEE Trans. VLSI Syst. 8, 3.
    • (2000) IEEE Trans. VLSI Syst. , vol.8 , pp. 3
    • Benini, L.1    Bogliolo, A.2    Micheli De, G.3
  • 15
    • 0034316208 scopus 로고    scopus 로고
    • Scalable hardware priority queue architectures for high-speed packet switches
    • Moon, S. W., Rexford, J., Shin, K. G., 2000. Scalable hardware priority queue architectures for high-speed packet switches.IEEE Trans. Comput. 49, 11.
    • (2000) IEEE Trans. Comput. , vol.49 , pp. 11
    • Moon, S.W.1    Rexford, J.2    Shin, K.G.3
  • 18
    • 0036705054 scopus 로고    scopus 로고
    • HW/SW codesign techniques for dynamically reconfigurable architectures
    • Noguera, J., Badia, R. M., 2002. HW/SW codesign techniques for dynamically reconfigurable architectures.IEEE Trans. VLSI Syst. 10, 4.
    • (2002) IEEE Trans. VLSI Syst. , vol.10 , pp. 4
    • Noguera, J.1    Badia, R.M.2
  • 20
    • 0032686439 scopus 로고    scopus 로고
    • Temporal partitioning and scheduling data flow graphs for reconfigurable computers
    • Purna, K., Bhatia, D., 1999. Temporal partitioning and scheduling data flow graphs for reconfigurable computers.IEEE Trans. Comput. 48, 6.
    • (1999) IEEE Trans. Comput. , vol.48 , pp. 6
    • Purna, K.1    Bhatia, D.2
  • 28
    • 0034828230 scopus 로고    scopus 로고
    • Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform
    • Copenhagen, Denmark
    • Wong, C., et al. 2001. Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform.In Proceedings of International Symposium on Hardware/Software Codesign (CODES'01), Copenhagen, Denmark.
    • (2001) In Proceedings of International Symposium on Hardware/Software Codesign (CODES'01
    • Wong, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.