-
1
-
-
0031708530
-
Scheduling for embedded real-time systems
-
15 (Jan.-Mar.
-
Balarin, F. et al. 1998. Scheduling for embedded real-time systems.IEEE Des. Test Comput. 15 (Jan.-Mar.), 1.
-
(1998)
IEEE Des. Test Comput.
, pp. 1
-
-
Balarin, F.1
-
2
-
-
0033706197
-
A survey of design techniques for system-level dynamic power management
-
Benini, L., Bogliolo, A., Micheli De., G. 2000. A survey of design techniques for system-level dynamic power management.IEEE Trans. VLSI Syst. 8, 3.
-
(2000)
IEEE Trans. VLSI Syst.
, vol.8
, pp. 3
-
-
Benini, L.1
Bogliolo, A.2
Micheli De, G.3
-
5
-
-
0032308182
-
CORDS: Hardware-software co-synthesis of reconfigurable realtime distributed embedded systems
-
San Jose, CA, USA
-
Dick, R. P., Jha, N. K., 1998. CORDS: Hardware-software co-synthesis of reconfigurable realtime distributed embedded systems. In Proceedings ofInternational Conference Computer Aided Design (ICCAD'98), San Jose, CA, USA.
-
(1998)
Proceedings ofInternational Conference Computer Aided Design (ICCAD'98
-
-
Dick, R.P.1
Jha, N.K.2
-
6
-
-
0031681657
-
TGFF: Task graphs for free
-
Seattle, WA, USA
-
Dick, P., Rhodes, D.L., Wolf, W., 1998. TGFF: Task graphs for free. In Proceedings International. Workshop Hardware/Software Codesign, Seattle, WA, USA.
-
(1998)
Proceedings International. Workshop Hardware/Software Codesign
-
-
Dick, P.1
Rhodes, D.L.2
Wolf, W.3
-
7
-
-
0033698642
-
Power analysis of embedded operating systems
-
Los Angeles, CA, USA
-
Dick, R. P., Lakshminarayana, G., Raghunathan, A., Jha, N. K., 2000. Power analysis of embedded operating systems. In Proceeding Design Automation Conference (DAC), Los Angeles, CA, USA.
-
(2000)
Proceeding Design Automation Conference (DAC
-
-
Dick, R.P.1
Lakshminarayana, G.2
Raghunathan, A.3
Jha, N.K.4
-
8
-
-
0034187808
-
Dynamic scheduling of tasks on partially reconfigurable FPGAs
-
Diessel, O., Elgindy, H., Middendorf, M., Schmeck, H., Schmidt, B., 2000. Dynamic scheduling of tasks on partially reconfigurable FPGAs.IEE Proceedings-Computers and Digital Techniques, Institution of Electrical Engineers, 147(3).
-
(2000)
IEE Proceedings-Computers and Digital Techniques, Institution of Electrical Engineers
, vol.147
, Issue.3
-
-
Diessel, O.1
Elgindy, H.2
Middendorf, M.3
Schmeck, H.4
Schmidt, B.5
-
13
-
-
62349131597
-
Preemptive multitasking on FPGAs
-
Napa, CA, USA
-
Levinson, L., Manner, R., Sessler, M., Simmler, H., 2000. Preemptive multitasking on FPGAs. In Proceedings Symposium on Field-Programmable Custom Computing Machines (FCCM'00), Napa, CA, USA.
-
(2000)
Proceedings Symposium on Field-Programmable Custom Computing Machines (FCCM'00
-
-
Levinson, L.1
Manner, R.2
Sessler, M.3
Simmler, H.4
-
15
-
-
0034316208
-
Scalable hardware priority queue architectures for high-speed packet switches
-
Moon, S. W., Rexford, J., Shin, K. G., 2000. Scalable hardware priority queue architectures for high-speed packet switches.IEEE Trans. Comput. 49, 11.
-
(2000)
IEEE Trans. Comput.
, vol.49
, pp. 11
-
-
Moon, S.W.1
Rexford, J.2
Shin, K.G.3
-
18
-
-
0036705054
-
HW/SW codesign techniques for dynamically reconfigurable architectures
-
Noguera, J., Badia, R. M., 2002. HW/SW codesign techniques for dynamically reconfigurable architectures.IEEE Trans. VLSI Syst. 10, 4.
-
(2002)
IEEE Trans. VLSI Syst.
, vol.10
, pp. 4
-
-
Noguera, J.1
Badia, R.M.2
-
19
-
-
0036042430
-
Dynamic run-time HW/SW scheduling techniques for dynamically reconfigurable architectures
-
Estes Park, CO, USA
-
Noguera, J., Badia, R. M., 2002. Dynamic run-time HW/SW scheduling techniques for dynamically reconfigurable architectures. In Proceedings of International Symposium on Hardware/Software Codesign (CODES'02), Estes Park, CO, USA.
-
(2002)
Proceedings of International Symposium on Hardware/Software Codesign (CODES'02
-
-
Noguera, J.1
Badia, R.M.2
-
20
-
-
0032686439
-
Temporal partitioning and scheduling data flow graphs for reconfigurable computers
-
Purna, K., Bhatia, D., 1999. Temporal partitioning and scheduling data flow graphs for reconfigurable computers.IEEE Trans. Comput. 48, 6.
-
(1999)
IEEE Trans. Comput.
, vol.48
, pp. 6
-
-
Purna, K.1
Bhatia, D.2
-
21
-
-
3042640630
-
A comparison of five different multiprocessor SoC bus architectures
-
Warsaw, Poland
-
Ryu, K., Shin, E., Mooney, V., 2001. A comparison of five different multiprocessor SoC bus architectures. In Proceedings of the EUROMICRO Symposium on Digital Systems Design (EU-ROMICRO'01), Warsaw, Poland.
-
(2001)
Proceedings of the EUROMICRO Symposium on Digital Systems Design (EU-ROMICRO'01
-
-
Ryu, K.1
Shin, E.2
Mooney, V.3
-
23
-
-
33747870341
-
Automating production of run-time reconfigurable designs
-
Napa, CA, USA
-
Shirazi, N., Luk, W., Cheung, P., 1998. Automating production of run-time reconfigurable designs. In Proceedings of International Symposium Field-Programmable Custom Computing Machines (FCCM'98), Napa, CA, USA.
-
(1998)
Proceedings of International Symposium Field-Programmable Custom Computing Machines (FCCM'98
-
-
Shirazi, N.1
Luk, W.2
Cheung, P.3
-
24
-
-
0010786267
-
Multitasking on FPGA coprocessors
-
Villach, Austria
-
Simmler, H., Levinson, L., Manner, R., 2000. Multitasking on FPGA coprocessors. In Proceedings of 10th International Conference Field Programmable Logic and Applications (FPL2000), Villach, Austria.
-
(2000)
Proceedings of 10th International Conference Field Programmable Logic and Applications (FPL2000
-
-
Simmler, H.1
Levinson, L.2
Manner, R.3
-
28
-
-
0034828230
-
Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform
-
Copenhagen, Denmark
-
Wong, C., et al. 2001. Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform.In Proceedings of International Symposium on Hardware/Software Codesign (CODES'01), Copenhagen, Denmark.
-
(2001)
In Proceedings of International Symposium on Hardware/Software Codesign (CODES'01
-
-
Wong, C.1
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