Field-programmable custom computing machines - A taxonomy

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 79-88

  Sima, Mihai ^a,b   Vassiliadis, Stamatis ^a   Cotofana, Sorin ^a   Van Eijndhoven, Jos T J ^b   Vissers, Kees ^c  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c TriMedia Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; COMPUTERS; MICROPROGRAMMING; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; TAXONOMIES;

COMPUTING FACILITIES; COMPUTING PARADIGM; FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES; HARDWARE PLATFORM; RECONFIGURABLE COMPUTING; SOFTWARE CONTROL;

COMPUTATION THEORY;

EID: 79955133514     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_10     Document Type: Conference Paper

References (47)

1. C. Alippi, W. Fornaciari, L. Pozzi, and M. Sami. A DAG-Based Design Approach for Re-configurable VLIW Processors. In IEEE Design and Test Conference in Europe, Munich, Germany, 1999.
2. P. Athanas and H. Silverman. Processor Reconfiguration through Instruction-Set Metamorphosis. IEEE Computer, 26(3):11-18, 1993. (Pubitemid 23676019)
3. R. Bittner, Jr. and P. Athanas. Wormhole Run-time Reconfiguration. In Proc. Intl. Symp. on FPGAs, pp. 79-85, Monterey, California, 1997.
4. G.A. Blaauw and F.P. Brooks, Jr. Computer Architecture. Concepts and Evolution. Addison-Wesley, Reading, Massachusetts, 1997.
5. G. Brebner. Field-Programmable Logic: Catalyst for New Computing Paradigms. In Proc. Intl. Workshop FPL'98, pp. 49-58, Tallin, Estonia, 1998. (Pubitemid 128125201)
6. S. Brown and J. Rose. Architecture of FPGAs and CPLDs: A Tutorial. IEEE Transactions on Design and Test of Computers, 13(2):42-57, 1996.
7. D.A. Buell and K.L. Pocek. Custom Computing Machines: An Introduction. Journal of Supercomputing, 9(3):219-230, 1995.
8. S. Cadambi et al. Managing Pipeline-Reconfigurable FPGAs. In Proc. Intl. Symp. on FPGAs, pp. 55-64, Monterey, California, 1998.
9. S. Casselman. Virtual Computing and the Virtual Computer. In Proc. IEEE Workshop on FCCMs, pp. 43-48, Napa Valley, California, 1993.
10. D. Cronquist et al. Architecture Design of Reconfigurable Pipelined Datapaths. Advanced Research in VLSI, pp. 23-40, 1999.
11. A. DeHon. Reconfigurable Architectures for General-Purpose Computing. A. I. 1586, Massachusetts Institute of Technology, Cambridge, Massachusetts, 1996.
12. A. Donlin. Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry. In Proc. Intl. Workshop FPL'98, pp. 199-208, Tallin, Estonia, 1998. (Pubitemid 128125216)
13. M. J. Flynn. Some Computer Organizations and Their Effectiveness. IEEE Transactions on Computers, C-21(9):948-960, September 1972.
14. K.L. Gilson. Integrated Circuit Computing Device Comprising a Dynamically Configurable Gate Array Having a Microprocessor and Reconfigurable Instruction Execution Means and Method Therefor. U.S. Patent No. 5,361,373, 1994.
15. S. Guccione and M. Gonzales. Classification and Performance of Reconfigurable Architectures. In Proc. Intl. Workshop FPL'95, pp. 439-448, Oxford, United Kingdom, 1995.
16. R. Hartenstein, Becker, and R. Kress. Custom Computing Machines versus Hardware/Software Co-Design: From a Globalized Point of View. In Proc. Intl. Workshop FPL'96, pp. 65-76, Darmstadt, Germany, 1996. (Pubitemid 126136663)
17. R. Hartenstein et al. A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance Hardware. Future Generation Computer Systems, (7):181-198, 1991/1992.
18. R. Hartenstein, R. Kress, and H. Reinig. A New FPGA Architecture for Word-Oriented Datapaths. In Proc. Intl. Workshop FPL'94, pp. 144-155, Prague, Czech Republic, 1994.
19. S. Hauck. The Roles of FPGA's in Reprogrammable Systems. Proc. of the IEEE, 86(4):615-638, 1998. (Pubitemid 128720219)
20. S. Hauck, T.W. Fry, M.M. Hosler, and J.P. Kao. The Chimaera Reconfigurable Functional Unit. In Proc. IEEE Symp. on FCCMs, pp. 87-96, Napa Valley, California, 1997.
21. J. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In Proc. IEEE Symp. on FCCMs, pp. 12-21, Napa Valley, California, 1997.
22. C. Iseli and E. Sanchez. A Superscalar and Reconfigurable Processor. In Proc. Intl. Workshop FPL'94, pp. 168-174, Prague, Czech Republic, 1994.
23. J. Jacob and P. Chow. Memory Interfacing and Instruction Specification for Reconfigurable Processors. In Proc. Intl. ACM/SIGDA Symp. on FPGAs, pp. 145-154, Monterey, California, 1999.
24. D. Jones and D. Lewis. A Time-Multiplexed FPGA Architecture for Logic Emulation. In Proc. IEEE CICC'95, pp. 487-494, Santa Clara, California, 1995.
25. B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In Proc. IEEE Symp. on FCCMs, pp. 92-100, Napa Valley, California, 1999.
26. B. Kastrup, J. van Meerbergen, and K. Nowak. Seeking (the right) Problems for the Solutions of Reconfigurable Computing. In Proc. Intl. Workshop FPL'99, pp. 520-525, Glasgow, Scotland, 1999.
27. A. Lew and R. Halverson, Jr. A FCCM for Dataflow (Spreadsheet) Programs. In Proc. IEEE Symp. on FCCMs, pp. 2-10, Napa Valley, California, 1995.
28. W. Mangione-Smith and B. Hutchings. Reconfigurable Architectures: The Road Ahead. In Reconfigurable Architectures Workshop, pp. 81-96, Geneva, Switzerland, 1997.
29. W. Mangione-Smithetal. Seeking Solutions in Configurable Computing. IEEE Computer, 30(12):38-43, 1997.
30. T. Miyamori and K. Olukotun. A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. In Proc. IEEE Symp. on FCCMs, pp. 2-11, Napa Valley, California, 1998.
31. B. Radunović and V Milutinović. A Survey of Reconfigurable Computing Architectures. In Proc. Intl. Workshop FPL'98, pp. 376-385, Tallin, Estonia, 1998. (Pubitemid 128125234)
32. T. Rauscher and P. Adams. Microprogramming: A Tutorial and Survey of Recent Developments. IEEE Transactions on Computers, C-29(1):2-20, 1980. (Pubitemid 10449021)
33. R. Razdan and M. Smith. A High Performance Microarchitecture with Hardware-Programmable Functional Units. In Proc. 27th Annual Intl. Symp. on Microarchitecture, pp. 172-180, San Jose, California, 1994.
34. C. Rupp et al. The NAPA Adaptive Processing Architecture. In Proc. IEEE Symp. on FCCMs, pp. 28-37, Napa Valley, California, 1998.
35. Z. Salcic and B. Maunder. CCSimP - An Instruction-Level Custom-Configurable Processor for FPLDs. In Proc. Intl. Workshop FPL'96, pp. 280-289, Darmstadt, Germany, 1996. (Pubitemid 126136686)
36. S. Sawitzki, A. Gratz, and R.G. Spallek. Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. In Proc. Intl. Workshop FPL'98, pp. 411-415, Tallin, Estonia, 1998. (Pubitemid 128125240)
37. M. Sima, S. Cotofana, J.T. van Eijndhoven, S. Vassiliadis, and K. Vissers. 8 × 8 IDCT Implementation on an FPGA-augmented TriMedia. In Proc. IEEE Symp. on FCCMs, Rohnert Park, California, 2001.
38. H. Singh et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Application. IEEE Tran. on Computers, 49(5):465-481, 2000.
39. S. Trimberger. Reprogrammable Instruction Set Accelerator. U.S. Patent No. 5,737,631, 1998.
40. S. Trimberger. Reprogrammable Instruction Set Accelerator Using a Plurality of Programmable Execution Units and an Instruction Page Table. U.S. Patent No. 5,748,979, 1998.
41. S. Vassiliadis, S. Wong, and S. Cotofana. The MOLEN rm-coded Processor. In Proc. Intl. Workshop FPL-2001, pp. 275-415, Belfast, N. Ireland, U.K., 2001.
42. J. Villasenor and W. Mangione-Smith. Configurable Computing. Scientific American, pp. 55-59, 1997.
43. M. Wazlowski et al. PRISM-II Compiler and Architecture. In Proc. IEEE Workshop on FCCMs, pp. 9-16, Napa Valley, California, 1993.
44. M. Wazlowski. A Reconfigurable Architecture Superscalar Coprocesor. PhD thesis, Brown University, Providence, Rhode Island, 1996.
45. M. Wirthlin and B. Hutchings. A Dynamic Instruction Set Computer. In Proc. IEEE Symp. on FCCMs, pp. 99-109, Napa Valley, California, 1995.
46. M. Wirthlin, B.L. Hutchings, and K.L. Gilson. The Nano Processor: A Low Resource Reconfigurable Processor. In Proc. IEEE Workshop on FCCMs, pp. 23-30, Napa Valley, California, 1994.
47. R. Wittig and P. Chow. One Chip: An FPGA Processor With Reconfigurable Logic. In Proc. IEEE Symp. on FCCMs, pp. 126-135, Napa Valley, California, 1996.