A reconfigurable multi-threaded architecture model

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2823, Issue , 2003, Pages 193-207

  Wallner, Sebastian ^a  

^a HAMBURG UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Computation Threads; Datapath Processor; Hardware Visualization; Pipelining; Reconfigurable Architectures

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; HARDWARE; PIPE LININGS; RECONFIGURABLE HARDWARE; VIRTUAL REALITY;

APPLICATION SPECIFIC HARDWARES; DATA PATHS; GENERAL-PURPOSE MICROPROCESSORS; HARDWARE VIRTUALIZATION; MULTITHREADED ARCHITECTURE; PERFORMANCE AND APPLICATIONS; PROPOSED ARCHITECTURES; RECONFIGURABLE COMPUTING;

RECONFIGURABLE ARCHITECTURES;

EID: 35248899829     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39864-6_16     Document Type: Article

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