메뉴 건너뛰기




Volumn , Issue , 2007, Pages

Cost-driven hybrid configuration prefetching for partial reconfigurable coprocessor

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; PROBABILITY; PROGRAM PROCESSORS;

EID: 34548722028     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370384     Document Type: Conference Paper
Times cited : (5)

References (11)
  • 2
    • 0031360911 scopus 로고    scopus 로고
    • J. R. Hauser, Wawrzynek, J., 'Garp: A MIPS Processor with a Reconfigurable Coprocessor,' in Proc. IEEE Workshop FPGA's Custom Comput. Machiens, J. Anold and K. L. Pocek, Eds., Napa, CA, pp. 12-21, Apr. 1997.
    • J. R. Hauser, Wawrzynek, J., 'Garp: A MIPS Processor with a Reconfigurable Coprocessor,' in Proc. IEEE Workshop FPGA's Custom Comput. Machiens, J. Anold and K. L. Pocek, Eds., Napa, CA, pp. 12-21, Apr. 1997.
  • 4
    • 0036382691 scopus 로고    scopus 로고
    • Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation
    • Z. Li, and S. Hauck, 'Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation,' in ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 2002.
    • (2002) ACM/SIGDA Symposium on Field-Programmable Gate Arrays
    • Li, Z.1    Hauck, S.2
  • 8
    • 0036625327 scopus 로고    scopus 로고
    • Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing
    • K. Compton, et. al, 'Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing,' IEEE Transactions on VLSI Systems, 2002.
    • (2002) IEEE Transactions on VLSI Systems
    • Compton, K.1    et., al.2
  • 9
  • 10
    • 34548725000 scopus 로고    scopus 로고
    • www.simplescalar.com
  • 11
    • 34548712920 scopus 로고    scopus 로고
    • www.spec2000.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.