The MOLEN ρμ-coded processor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2147, Issue , 2001, Pages 275-285

  Vassiliadis, Stamatis ^a   Wong, Stephan ^a   Coţofană, Sorin ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; MOTION PICTURE EXPERTS GROUP STANDARDS;

CACHING MECHANISM; CYCLE TIME ESTIMATION; EXECUTION CYCLES; HARDWARE FEATURES; PARTIAL RECONFIGURATION; PERFORMANCE POTENTIALS; RECONFIGURATION CAPABILITY; SUPERSCALAR PROCESSOR;

BENCHMARKING;

EID: 84949189232     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44687-7_29     Document Type: Conference Paper

References (15)

1. J. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor,” in Proceedings of the IEEE Symposium of Field-Programmable Custom Computing Machines, pp. 24–33, April 1997.
2. J. M. Rabaey, “Reconfigurable Computing: The Solution to Low Power Programmable DSP,” in Proceedings 1997 ICASSP Conference, (Munich), April 1997.
3. D. C. Burger and T. M. Austin, “The SimpleScalar Tool Set, Version 2.0,” Technical Report CS-TR-1997-1342, University of Wisconsin-Madison, 1997.
4. “Virtex-II 1.5V FPGA Family: Detailed Functional Description.” http://www.xilinx.com/partinfo/databook.htm.
5. C. Loeffler, A. Ligtenberg, and G. Moschytz, “Practical Fast 1-D DCT Algorithms With 11 Multiplications,” in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, pp. 988–991, 1989.
6. R. Razdan, PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, Cambridge, Massachusetts, May 1994.
7. S. A. Hauck, “Configuration Prefetch for Single Context Reconfigurable Coprocessors,” in 6th Int. Symposium on Field Programmable Gate Arrays, pp. 65–74, February 1998.
8. R. D. Wittig and P. Chow, “OneChip: An FPGA Processor With Reconfigurable Logic,” in IEEE Symposium on FPGAs for Custom Computing Machines (K. L. Pocek and J. M. Arnold, eds.), (Napa Valley, California), pp. 126–135, April 1996.
9. S. M. Trimberger, “Reprogrammable Instruction Set Accelerator.” U.S. Patent No. 5,737,631, April 1998.
10. J. R. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor,” in IEEE Symposium on FPGAs for Custom Computing Machines, (Napa Valley, California), pp. 12–21, April 1997.
11. P. M. Athanas and H. F. Silverman, “Processor Reconfiguration through Instruction-Set Metamorphosis,” IEEE Computer, vol. 26, pp. 11–18, March 1993.
12. K. L. Gilson, “Integrated Circuit Computing Device Comprising a Dynamically Configurable Gate Array Having a Reconfigurable Execution Means.” WO Patent No. 94/14123, June 1994.
13. H. Schmit, “Incremental Reconfiguration for Pipelined Applications,” in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 47–55, April 1997.
14. S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer, “PipeRench: A Coprocessor for Streaming Multimedia Acceleration,” in The 26th International Symposium on Computer Architecture, (Atlanta, Georgia), pp. 28–39, May 1999.
15. R.W. Hartenstein, R. Kress, and H. Reinig, “A New FPGA Architecture forWord-Oriented Datapaths,” in Proceeding of the 4th International Workshop on Field-Programmable Logic and Applications: Architectures, Synthesis and Applications., pp. 144–155, September 1994.