The Erlangen slot machine: A dynamically reconfigurable FPGA-based computer

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 47, Issue 1, 2007, Pages 15-31

  Majer, Mateusz ^a   Teich, Jürgen ^a   Ahmadinia, Ali ^b   Bobda, Christophe ^c  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^b Inst for Infrastructure and Environment   (United Kingdom)

^c Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

ESM; FPGA based computer; Partiall dynamic reconfiguration; Platform; Rekonfiguration manager; Relocation

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPTIMIZATION; TELECOMMUNICATION SYSTEMS;

FPGA BASED COMPUTER; HARDWARE MODULE RELOCATION; PARTIALL DYNAMIC RECONFIGURATION; RECONFIGURATION MANAGER;

COMPUTER SYSTEMS;

EID: 34247607804     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11265-006-0017-6     Document Type: Conference Paper

References (34)

1. P. Schaumont, I. Verbauwhede, K. Keutzer, and M. Sarrafzadeh, "A Quick Safari through the Reconfiguration Jungle," in Proc. of the 38th Design Automation Conference, Las Vegas, 2001, pp. 127-177.
2. J. O. Kephart and D. M. Chess, "The Vision of Autonomic Computing," Computer, vol. 36, 2003, pp. 41-52.
3. IBM Autonomic Computing Initiative, (http://www.research.ibm.com/ autonomic/).
4. C. Müller-Schloer, C. von der Malsburg, and R. P. Würtz, "Organic Computing," Inform.-Spektrum, vol. 27, 2004, pp. 332-336.
5. The Organic Computing Page, (http://www.organic-computing.org).
6. SPP1148 Reconfigurable Computing Priority Program, (http://www12. informatik.uni-erlangen.de/spprr/).
7. A. Ahmadinia, C. Bobda, S. Fekete, J. Teich, and J. van der Veen, "Optimal Routing-conscious Dynamic Placement for Reconfigurable Devices," in Proc. of International Conference on Field-Programmable Logic and Applications. Lecture Notes in Computer Science (LNCS), vol. 3203, Antwerp, Belgium, Springer, 2004, pp. 847-851.
8. K. Bazargan, R. Kastner, and M. Sarrafzadeh, "Fast Template Placement for Reconfigurable Computing Systems," IEEE Des. Test Comput., vol. 17, 2000, pp. 68-83.
9. M. Majer, J. Teich, and C. Bobda, "ESM - the Erlangen Slot Machine," (http://www.r-space.de).
10. C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth, J. Teich, S. P. Fekete, and J. van der Veen, "The Erlangen Slot Machine: A Highly Flexible FPGA-based Reconfigurable Platform," in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, 2005, pp. 319-320.
11. C. Bobda, A. Ahmadinia, M. Majer, J. Ding, and J. Teich, "Modular Video Streaming on a Reconfigurable Platform," in Proc. of the IFIP International Conference on Very Large Scale Integration, Perth, Australia, 2005, pp. 103-108.
12. C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth, and J. Teich, "Increasing the Flexibility in FPGA-based Reconfigurable Platforms: The Erlangen Slot Machine," in Proc. IEEE Conference on Field-Programmable Technology, Singapore, Singapore, 2005, pp. 37-42.
13. Y. Krasteva, A. Jimeno, E. Torre, and T. Riesgo, "Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs," in Proc. of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, 2005, pp. 77-83.
14. V. Baumgarte, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, "PACT XPP - a Self-reconfigurable Data Processing Architecture," in ERSA, Las Vegas, Nevada, 2001, pp. 167-184.
15. Silicon Hive, (http://www.siliconhive.com).
16. PicoChip, (http://www.picochip.com).
17. Elixent Ltd., (http://www.elixent.com).
18. NEC DRP Project, (http://www.necel.com/en/techhighlights/drp/).
19. Xilinx, Inc., (http://www.xilinx.com).
20. Celoxica Ltd., RC2000 Development Board, 2004.
21. Xess Corp., (http://www.xess.com).
22. Nallatech, Inc., (http://www.nallatech.com).
23. Alpha Data Ltd., ADM-XRC-II Xilinx Virtex-II PMC, 2002.
24. M. Platzner and L. Thiele, XFORCES - executives for Reconfigurable Embedded Systems, (http://www.ee.ethz.ch/platzner).
25. C. Steiger, H. Walder, M. Platzner, and L. Thiele, "Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices," in Proc. of the 24th International Real-Time Systems Symposium, Cancun, Mexico, 2003, pp. 224-235.
26. H. Kalte, M. Porrmann, and U. Rückert, "A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs," in Proc. IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.
27. C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen, "DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices," in Proc. of the International Conference on Field-Programmable Logic and Applications, Tampere, Finland, 2005, pp. 153-158.
28. P. Lysaght, B. Blodge, J. Mason, J. Young, and B. Bridgeford, "Enhanced Architectures, Design Methodologies and Cad Tools for Dynamic Reconfiguration of Xilinx FPGAs," in Proc. of 16th International Conference on Field Programmable Logic and Applications (FPL06), Madrid, Spain, 2006.
29. A. Ahmadinia, J. Ding, C. Bobda, and J. Teich, "Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC)," Technical Report 02-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, 2004.
30. S. Fekete, J. van der Veen, M. Majer, and J. Teich, "Minimizing Communication Cost for Reconfigurable Slot Modules," in Proceedings of 16th International Conference on Field Programmable Logic and Applications (FPL06), Madrid, Spain, 2006.
31. H. A. ElGindy, A. K. Somani, H. Schröder, H. Schmeck, and A. Spray, "RMB - a Reconfigurable Multiple Bus Network," in Proc. of the Second International Symposium on High-Performance Computer Architecture (HPCA-2), San Jose, California, 1996, pp. 108-117.
32. R. Vaidyanathan and J. L. Trahan, Dynamic Reconfiguration: Architectures and Algorithms, IEEE Computer Society, 2003.
33. A. Ahmadinia, C. Bobda, J. Ding, M. Majer, J. Teich, S. Fekete, and J. van der Veen, "A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices," in Proc. of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, 2005, pp. 84-90.
34. R. Gonzalez and R. Woods, Digital Image Processing, Prentice Hall, 2002.