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Volumn , Issue , 2009, Pages 982-987

Automated data analysis solutions to silicon debug

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED DATA ANALYSIS; DEBUG TECHNIQUES; DESIGN ERRORS; FUNCTIONAL VERIFICATION; RUNTIMES; SILICON DEBUG; SOFTWARE SOLUTION; TEMPORAL DOMAIN; TEST ENVIRONMENT; TEST SEQUENCE;

EID: 70350064446     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (21)

References (17)
  • 1
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    • A survey of techniques for formal verification of combinational circuits
    • Oct
    • J. Jan, A. Narayan, M. Fujita, and A. S. Vincentelli, "A survey of techniques for formal verification of combinational circuits," in Int'l Conf. on Comp. Design, Oct. 1997, pp. 445-454.
    • (1997) Int'l Conf. on Comp. Design , pp. 445-454
    • Jan, J.1    Narayan, A.2    Fujita, M.3    Vincentelli, A.S.4
  • 2
    • 1942500401 scopus 로고    scopus 로고
    • Safety property verification using sequential SAT and bounded model checking
    • March
    • G. Parthasarathy, M. K. Iyer, K.-T. Cheng, and L.-C. Wang, "Safety property verification using sequential SAT and bounded model checking," IEEE Design & Test of Comp., vol. 21, no. 2, pp. 132-143, March 2004.
    • (2004) IEEE Design & Test of Comp , vol.21 , Issue.2 , pp. 132-143
    • Parthasarathy, G.1    Iyer, M.K.2    Cheng, K.-T.3    Wang, L.-C.4
  • 3
    • 0030679993 scopus 로고    scopus 로고
    • Toward formalizing a validation methodology using simulation coverage
    • June
    • A. Gupta, S. Malik, and P. Ashar, "Toward formalizing a validation methodology using simulation coverage," in Design Automation Conf., June 1997, pp. 740-745.
    • (1997) Design Automation Conf , pp. 740-745
    • Gupta, A.1    Malik, S.2    Ashar, P.3
  • 4
    • 70350048545 scopus 로고    scopus 로고
    • Virtually every ASIC ends up an FPGA
    • EETimes.com, Dec. 7
    • J. Jaeger, "Virtually every ASIC ends up an FPGA," EETimes.com, Dec. 7 2007.
    • (2007)
    • Jaeger, J.1
  • 7
    • 3142636922 scopus 로고    scopus 로고
    • Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction
    • July
    • P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, "Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction," IEEE Trans. on CAD, vol. 23, no. 7, pp. 1142-1153, July 2004.
    • (2004) IEEE Trans. on CAD , vol.23 , Issue.7 , pp. 1142-1153
    • Rosinger, P.M.1    Al-Hashimi, B.M.2    Nicolici, N.3
  • 9
    • 34548336884 scopus 로고    scopus 로고
    • Low cost debug architecture using lossy compression for silicon debug
    • April
    • E. Anis and N. Nicolici, "Low cost debug architecture using lossy compression for silicon debug," in Proc. of Design, Automation and Test in Europe, April 2007, pp. 1-6.
    • (2007) Proc. of Design, Automation and Test in Europe , pp. 1-6
    • Anis, E.1    Nicolici, N.2
  • 10
    • 33847169370 scopus 로고    scopus 로고
    • Microprocessor silicon debug based on failure propagation tracing
    • Oct
    • O. Caty, P. Dahlgren, and I. Bayraktaroglu, "Microprocessor silicon debug based on failure propagation tracing," in Proc. of Int'l Test Conf., Oct. 2005, pp. 1-10.
    • (2005) Proc. of Int'l Test Conf , pp. 1-10
    • Caty, O.1    Dahlgren, P.2    Bayraktaroglu, I.3
  • 12
    • 0031378505 scopus 로고    scopus 로고
    • A deductive technique for diagnosis for bridging faults
    • Nov
    • S. Venkataraman and W. K. Fuchs, "A deductive technique for diagnosis for bridging faults," in Proc. of Int'l Conf. on CAD, Nov. 1997, pp. 562-567.
    • (1997) Proc. of Int'l Conf. on CAD , pp. 562-567
    • Venkataraman, S.1    Fuchs, W.K.2
  • 13
    • 33746884718 scopus 로고    scopus 로고
    • Extraction error modeling and automated model debugging in high-performance custom designs
    • July
    • Y. Yang, A. Veneris, P. Thadikaran, and S. Venkataraman, "Extraction error modeling and automated model debugging in high-performance custom designs," IEEE Trans. on VLSI Systems, vol. 14, no. 7, pp. 763-776, July 2006.
    • (2006) IEEE Trans. on VLSI Systems , vol.14 , Issue.7 , pp. 763-776
    • Yang, Y.1    Veneris, A.2    Thadikaran, P.3    Venkataraman, S.4
  • 15
    • 0345869803 scopus 로고    scopus 로고
    • Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
    • Jan
    • L. Huisman, "Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)," IEEE Trans. on CAD, vol. 23, no. 1, pp. 91-101, Jan. 2004.
    • (2004) IEEE Trans. on CAD , vol.23 , Issue.1 , pp. 91-101
    • Huisman, L.1
  • 17
    • 0032317509 scopus 로고    scopus 로고
    • Modeling the unknown! towards model-independent fault and error diagnosis
    • Oct
    • V. Boppana and M. Fujita, "Modeling the unknown! towards model-independent fault and error diagnosis," in Proc. of Int'l Test Conf., Oct. 1998, pp. 1094-1101.
    • (1998) Proc. of Int'l Test Conf , pp. 1094-1101
    • Boppana, V.1    Fujita, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.