Survey of techniques for formal verification of combinational circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 445-454

  Jain, Jawahar ^a   Narayan, Amit ^a   Fujita, M ^a   Sangiovanni Vincentelli, A ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; DECISION THEORY; EQUIVALENT CIRCUITS; FORMAL LOGIC;

DECISION DIAGRAMS; FORMAL VERIFICATION;

COMBINATORIAL CIRCUITS;

EID: 0031364294     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (68)