Extraction error modeling and automated model debugging in high-performance custom designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 7, 2006, Pages 763-775

  Yang, Yu Shen ^a,b   Veneris, Andreas ^a,b   Thadikaran, Paul ^a,c   Venkataraman, Srikanth ^a,c  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c INTEL CORPORATION   (United States)

Author keywords

Debugging; Errors; Extraction; Test model; VLSI

Indexed keywords

DEBUGGING; TEST MODEL; TIME-CONSUMING PROCESS; VLS;

ERRORS; EXTRACTION; FORMAL LOGIC; INFORMATION ANALYSIS; MATHEMATICAL MODELS;

PROGRAM DEBUGGING;

EID: 33746884718     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878346     Document Type: Conference Paper

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