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Volumn , Issue , 2006, Pages 94-97

Diagnosing silicon failures based on functional test patterns

Author keywords

Design for debug; Fault diagnosis; Silicon debug

Indexed keywords

FAILURE ANALYSIS; MICROPROCESSOR CHIPS;

EID: 46449083793     PISSN: 15504093     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTV.2006.9     Document Type: Conference Paper
Times cited : (10)

References (7)
  • 1
    • 0036575031 scopus 로고    scopus 로고
    • Design for Debug: Catching Design Errors in Digital Chips
    • May-June
    • B. Vermeulen and S. K. Goel, "Design for Debug: Catching Design Errors in Digital Chips", IEEE Design & Test of Computers, May-June 2002.
    • (2002) IEEE Design & Test of Computers
    • Vermeulen, B.1    Goel, S.K.2
  • 6
    • 0035687352 scopus 로고    scopus 로고
    • Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm
    • ITC
    • T. Barternstein, D. Heaberlin, L. Huisman, and D. Sliwinski, "Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm", Proc. Int'l Test Conf. (ITC), 2001.
    • (2001) Proc. Int'l Test Conf
    • Barternstein, T.1    Heaberlin, D.2    Huisman, L.3    Sliwinski, D.4
  • 7
    • 0032306936 scopus 로고    scopus 로고
    • Novel Optical Probing Techniques for Flip-Chip Packaged Microprocessors
    • ITC
    • M. Paniccia, T. Eiles, V. R. M. Rao, and W-M. Yee, "Novel Optical Probing Techniques for Flip-Chip Packaged Microprocessors", Proc. Int'l Test Conf. (ITC), 1998.
    • (1998) Proc. Int'l Test Conf
    • Paniccia, M.1    Eiles, T.2    Rao, V.R.M.3    Yee, W.-M.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.