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Volumn , Issue , 2007, Pages 225-230

Low cost debug architecture using lossy compression for silicon debug

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COST EFFECTIVENESS; IMAGE COMPRESSION; INFORMATION DISSEMINATION; ITERATIVE DECODING;

EID: 34548336884     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364595     Document Type: Conference Paper
Times cited : (50)

References (22)
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    • Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
    • February
    • A. Hopkins and K. McDonald-Maier. Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores. IEEE Transactions on Computers, 55(2):174-184, February 2006.
    • (2006) IEEE Transactions on Computers , vol.55 , Issue.2 , pp. 174-184
    • Hopkins, A.1    McDonald-Maier, K.2
  • 13
    • 0032315255 scopus 로고    scopus 로고
    • FakeFault: A Silicon Debug Software Tool for Microprocessor Embedded Memory Arrays
    • October
    • Y-J. Kwon, B. Mathew, and H. Hao. FakeFault: A Silicon Debug Software Tool for Microprocessor Embedded Memory Arrays. In Proceedings IEEE International Test Conference (ITC), pages 727-732, October 1998.
    • (1998) Proceedings IEEE International Test Conference (ITC) , pp. 727-732
    • Kwon, Y.-J.1    Mathew, B.2    Hao, H.3
  • 15
    • 27844542862 scopus 로고    scopus 로고
    • An Embedded Debugging Architecture for SOCs
    • February
    • R. Leatherman and N. Stollon. An Embedded Debugging Architecture for SOCs. IEEE Potentials, 24(1):12-16, February 2005.
    • (2005) IEEE Potentials , vol.24 , Issue.1 , pp. 12-16
    • Leatherman, R.1    Stollon, N.2
  • 16
    • 0034510954 scopus 로고    scopus 로고
    • Emerging On-chip Debugging Techniques for Real-Time Embedded Systems
    • December
    • C. MacNamee and D. Heffernan. Emerging On-chip Debugging Techniques for Real-Time Embedded Systems. IEE Computing & Control Engineering Journal, 11(6):295-303, December 2000.
    • (2000) IEE Computing & Control Engineering Journal , vol.11 , Issue.6 , pp. 295-303
    • MacNamee, C.1    Heffernan, D.2
  • 17
    • 34548326843 scopus 로고    scopus 로고
    • On-Chip Debugging - Built-in Logic Analyzers on your FPGA
    • January
    • K. Morris. On-Chip Debugging - Built-in Logic Analyzers on your FPGA. Journal of FPGA and Structured ASIC, 2(3), January 2004.
    • (2004) Journal of FPGA and Structured ASIC , vol.2 , Issue.3
    • Morris, K.1
  • 19
    • 0027593771 scopus 로고
    • IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement
    • May
    • J. Solden and R. Anderson. IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement. Proceedings of the IEEE, 81(5):703-715, May 1993.
    • (1993) Proceedings of the IEEE , vol.81 , Issue.5 , pp. 703-715
    • Solden, J.1    Anderson, R.2
  • 20
    • 0031186690 scopus 로고    scopus 로고
    • IC Failure Analysis: The Importance of Test and Diagnostics
    • July
    • D. Vallett. IC Failure Analysis: The Importance of Test and Diagnostics. IEEE Design and Test of Computers, 14(4):76-82, July 1997.
    • (1997) IEEE Design and Test of Computers , vol.14 , Issue.4 , pp. 76-82
    • Vallett, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.