-
1
-
-
46149091986
-
Soft error derating computation in sequential circuits
-
H. Asadi and M. B. Tahoori. Soft error derating computation in sequential circuits. In ICCAD, pages 497-501, 2006.
-
(2006)
ICCAD
, pp. 497-501
-
-
Asadi, H.1
Tahoori, M.B.2
-
4
-
-
29344472607
-
-
D. Holcomb et al. Berkeley FIT estimation tool (BFIT). http://www.eecs. berkeley.edu/∼holcomb/BFIT.htm [5] R. Baumann. Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans. Device and Materials Reliability, 5(3):305-316, Sept. 2005.
-
D. Holcomb et al. Berkeley FIT estimation tool (BFIT). http://www.eecs. berkeley.edu/∼holcomb/BFIT.htm [5] R. Baumann. Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans. Device and Materials Reliability, 5(3):305-316, Sept. 2005.
-
-
-
-
5
-
-
0029752087
-
Critical charge calculations for a bipolar SRAM array
-
L. B. Freeman. Critical charge calculations for a bipolar SRAM array. IBM J. Res. Dev., 40(1):119-129, 1996.
-
(1996)
IBM J. Res. Dev
, vol.40
, Issue.1
, pp. 119-129
-
-
Freeman, L.B.1
-
6
-
-
51549113427
-
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
-
R. Garg et al. A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC'08, pages 918-923.
-
DAC'08
, pp. 918-923
-
-
Garg, R.1
-
7
-
-
0034450511
-
Impact of CMOS technology scaling on the atmospheric neutron soft error rate
-
Dec
-
P. Hazucha and C. Svensson. Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Trans. Nuclear Science, 47(6):2586-2594, Dec 2000.
-
(2000)
IEEE Trans. Nuclear Science
, vol.47
, Issue.6
, pp. 2586-2594
-
-
Hazucha, P.1
Svensson, C.2
-
8
-
-
45749142459
-
Phaser: Phased methodology for modeling the system-level effects of soft errors
-
May
-
J. A. Rivers et al. Phaser: Phased methodology for modeling the system-level effects of soft errors. IBM Journal of Research and Development, 52(3):293-306, May 2008.
-
(2008)
IBM Journal of Research and Development
, vol.52
, Issue.3
, pp. 293-306
-
-
Rivers, J.A.1
-
9
-
-
51549088435
-
On the role of timing masking in reliable logic circuit design
-
S. Krishnaswamy, et al. On the role of timing masking in reliable logic circuit design. DAC 2008, pages 924-929.
-
DAC 2008
, pp. 924-929
-
-
Krishnaswamy, S.1
-
10
-
-
0028112725
-
On latching probability of particle induced transients in combinational networks
-
P. Liden, et al. On latching probability of particle induced transients in combinational networks. FTCS 1994, pages 340-349.
-
FTCS 1994
, pp. 340-349
-
-
Liden, P.1
-
11
-
-
0034452351
-
Analysis of single-event effects in combinational logicsimulation of the AM2901 bitslice processor
-
Dec
-
L. Massengill, et al. Analysis of single-event effects in combinational logicsimulation of the AM2901 bitslice processor. IEEE Trans. Nuclear Science, 47(6):2609-2615, Dec 2000.
-
(2000)
IEEE Trans. Nuclear Science
, vol.47
, Issue.6
, pp. 2609-2615
-
-
Massengill, L.1
-
12
-
-
0036082034
-
Soft error rate mitigation techniques for modern microcircuits
-
D. Mavis and P. Eaton. Soft error rate mitigation techniques for modern microcircuits. Rel. Phy. Symp., pages 216-225, 2002.
-
(2002)
Rel. Phy. Symp
, pp. 216-225
-
-
Mavis, D.1
Eaton, P.2
-
13
-
-
84944062057
-
A model for transient fault propagation in combinatorial logic
-
July
-
M. Omana, et al. A model for transient fault propagation in combinatorial logic. IOLTS 2003, pages 111-115, July 2003.
-
(2003)
IOLTS
, vol.2003
, pp. 111-115
-
-
Omana, M.1
-
15
-
-
33847728638
-
Computing the soft error rate of a combinational logic circuit using parameterized descriptors
-
R. R. Rao, et al. Computing the soft error rate of a combinational logic circuit using parameterized descriptors. IEEE Trans. on CAD of Integ. Circ. and Sys., 26(3):468-479, 2007.
-
(2007)
IEEE Trans. on CAD of Integ. Circ. and Sys
, vol.26
, Issue.3
, pp. 468-479
-
-
Rao, R.R.1
-
16
-
-
84944403418
-
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
-
S. S. Mukherjee et al. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In MICRO 2003, pages 29-40.
-
(2003)
MICRO
, pp. 29-40
-
-
Mukherjee, S.S.1
-
17
-
-
34548308773
-
Verification-guided soft error resilience
-
S. A. Seshia, et al. Verification-guided soft error resilience. In DATE 2007, pages 1442-1447.
-
DATE 2007
, pp. 1442-1447
-
-
Seshia, S.A.1
-
18
-
-
0036931372
-
Modeling the effect of technology trends on soft error rate of combinational logic
-
P. Shivakumar, et al. Modeling the effect of technology trends on soft error rate of combinational logic, DSN'02, pp. 389-398.
-
DSN'02
, pp. 389-398
-
-
Shivakumar, P.1
-
19
-
-
84886730497
-
FASER: Fast analysis of soft error susceptibility for cell-based designs
-
B. Zhang, et al. FASER: fast analysis of soft error susceptibility for cell-based designs. ISQED 2006, pages 755-760.
-
ISQED 2006
, pp. 755-760
-
-
Zhang, B.1
-
20
-
-
33846595665
-
Sequential element design with built-in soft error resilience
-
Dec
-
M. Zhang, et al. Sequential element design with built-in soft error resilience. IEEE Transactions on VLSI, Dec. 2006.
-
(2006)
IEEE Transactions on VLSI
-
-
Zhang, M.1
-
23
-
-
0029732557
-
Terrestrial cosmic rays
-
January
-
J. Ziegler. Terrestrial cosmic rays. IBM J. Res. Develop, 40(1):pp19-39, January 1996.
-
(1996)
IBM J. Res. Develop
, vol.40
, Issue.1
, pp. 19-39
-
-
Ziegler, J.1
|