On latching probability of particle induced transients in combinational networks

Digest of Papers - International Symposium on Fault-Tolerant Computing

Volumn , Issue , 1994, Pages 340-349

  Liden, Peter ^a   Dahlgren, Peter ^a   Johansson, Rolf ^a   Karlsson, Johan ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MATHEMATICAL MODELS; PROBABILITY; TRANSIENTS;

COMBINATIONAL NETWORKS; ELECTRICAL MASKING; LATCHING PROBABILITY; LATCHING WINDOWS; PARTICLE INDUCED TRANSIENTS; SINGLE EVENT UPSETS;

COMBINATORIAL CIRCUITS;

EID: 0028112725     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)