-
1
-
-
0035167288
-
SOI capacitor-less 1T-DRAM concept
-
Oct
-
S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, "SOI capacitor-less 1T-DRAM concept," in Proc. IEEE Int. SOI Conf., Oct. 2001, pp. 153-154.
-
(2001)
Proc. IEEE Int. SOI Conf
, pp. 153-154
-
-
Okhonin, S.1
Nagoga, M.2
Sallese, J.M.3
Fazan, P.4
-
2
-
-
0036104766
-
Memory design using one-transistor gain cell on SOI
-
Feb
-
T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi, "Memory design using one-transistor gain cell on SOI," in Proc. ISSCC Dig. Tech. Papers, Feb. 2002, pp. 152-153.
-
(2002)
Proc. ISSCC Dig. Tech. Papers
, pp. 152-153
-
-
Ohsawa, T.1
Fujita, K.2
Higashi, T.3
Iwata, Y.4
Kajiyama, T.5
Asao, Y.6
Sunouchi, K.7
-
3
-
-
0036508259
-
Challenges and future directions for the scaling of dynamic random-access-memory (DRAM)
-
Mar.-May
-
J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens, "Challenges and future directions for the scaling of dynamic random-access-memory (DRAM)," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 187-212, Mar.-May 2002.
-
(2002)
IBM J. Res. Develop
, vol.46
, Issue.2-3
, pp. 187-212
-
-
Mandelman, J.A.1
Dennard, R.H.2
Bronner, G.B.3
DeBrosse, J.K.4
Divakaruni, R.5
Li, Y.6
Radens, C.J.7
-
4
-
-
46049102832
-
Floating body RAM technology and its scalability to 32 nm node and beyond
-
Dec
-
T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, and A. Nitayama, "Floating body RAM technology and its scalability to 32 nm node and beyond," in IEDM Tech. Dig., Dec. 2006, pp. 569-572.
-
(2006)
IEDM Tech. Dig
, pp. 569-572
-
-
Shino, T.1
Kusunoki, N.2
Higashi, T.3
Ohsawa, T.4
Fujita, K.5
Hatsuda, K.6
Ikumi, N.7
Matsuoka, F.8
Kajitani, Y.9
Fukuda, R.10
Watanabe, Y.11
Minami, Y.12
Sakamoto, A.13
Nishimura, J.14
Nakajima, H.15
Morikado, M.16
Inoh, K.17
Hamamoto, T.18
Nitayama, A.19
-
5
-
-
33947625047
-
A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability
-
Mar
-
T. Hamamoto, Y. Minami, T. Shino, N. Kusunoki, H. Nakajima, M. Morikado, T. Yamada, K. Inoh, A. Sakamoto, T. Higashi, K. Fujita, K. Hatsuda, T. Ohsawa, and A. Nitayama, "A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability," IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 563-571, Mar. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.3
, pp. 563-571
-
-
Hamamoto, T.1
Minami, Y.2
Shino, T.3
Kusunoki, N.4
Nakajima, H.5
Morikado, M.6
Yamada, T.7
Inoh, K.8
Sakamoto, A.9
Higashi, T.10
Fujita, K.11
Hatsuda, K.12
Ohsawa, T.13
Nitayama, A.14
-
6
-
-
57749205627
-
Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation
-
Oct
-
H. Furuhashi, T. Shino, T. Ohsawa, F. Matsuoka, T. Higashi, Y. Minami, H. Nakajima, K. Fujita, R. Fukuda, T. Hamamoto, and A. Nitayama, "Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation," in Proc. IEEE Int. SOI Conf., Oct. 2008, pp. 33-34.
-
(2008)
Proc. IEEE Int. SOI Conf
, pp. 33-34
-
-
Furuhashi, H.1
Shino, T.2
Ohsawa, T.3
Matsuoka, F.4
Higashi, T.5
Minami, Y.6
Nakajima, H.7
Fujita, K.8
Fukuda, R.9
Hamamoto, T.10
Nitayama, A.11
-
7
-
-
31344475509
-
Design of a 128-Mb SOI DRAM using the floating body cell (FBC)
-
Jan
-
T. Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, T. Shino, Y. Minami, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, S. Watanabe, S. Fujii, and T. Furuyama, "Design of a 128-Mb SOI DRAM using the floating body cell (FBC)," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 135-145, Jan. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.1
, pp. 135-145
-
-
Ohsawa, T.1
Fujita, K.2
Hatsuda, K.3
Higashi, T.4
Shino, T.5
Minami, Y.6
Nakajima, H.7
Morikado, M.8
Inoh, K.9
Hamamoto, T.10
Watanabe, S.11
Fujii, S.12
Furuyama, T.13
-
8
-
-
33847101893
-
A 333 MHz random cycle DRAM using the floating body cell
-
Sep
-
K. Hatsuda, K. Fujita, and T. Ohsawa, "A 333 MHz random cycle DRAM using the floating body cell," in Proc. IEEE Custom Integr. Circuit Conf., Sep. 2005, pp. 259-262.
-
(2005)
Proc. IEEE Custom Integr. Circuit Conf
, pp. 259-262
-
-
Hatsuda, K.1
Fujita, K.2
Ohsawa, T.3
-
9
-
-
70349291207
-
A 2 ns-read-latency 4 Mb embedded floating body memory macro in 45 nm SOI technology
-
Feb
-
A. P. Singh, M. K. Ciraula, D. R. Weiss, J. J. Wuu, P. Bauser, P. de Champs, H. Daghighian, D. Fisch, P. Graber, and M. Bron, "A 2 ns-read-latency 4 Mb embedded floating body memory macro in 45 nm SOI technology," in Proc. ISSCC Dig. Tech. Papers, Feb. 2009, pp. 460-461.
-
(2009)
Proc. ISSCC Dig. Tech. Papers
, pp. 460-461
-
-
Singh, A.P.1
Ciraula, M.K.2
Weiss, D.R.3
Wuu, J.J.4
Bauser, P.5
de Champs, P.6
Daghighian, H.7
Fisch, D.8
Graber, P.9
Bron, M.10
-
10
-
-
57149124361
-
Enhancement of data retention time for 512-Mb DRAMs using high-pressure deuterium annealing
-
Dec
-
H. S. Chang and H. Hwang, "Enhancement of data retention time for 512-Mb DRAMs using high-pressure deuterium annealing," IEEE Trans. Electron Devices, vol. 55, no. 12, pp. 3599-3601, Dec. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.12
, pp. 3599-3601
-
-
Chang, H.S.1
Hwang, H.2
-
11
-
-
0142154824
-
A new block refresh concept for SOI floating body memories
-
Sep
-
P. Fazan, S. Okhonin, and M. Nagoga, "A new block refresh concept for SOI floating body memories," in Proc. IEEE Int. SOI Conf., Sep. 2003, pp. 15-16.
-
(2003)
Proc. IEEE Int. SOI Conf
, pp. 15-16
-
-
Fazan, P.1
Okhonin, S.2
Nagoga, M.3
-
12
-
-
64549104147
-
Autonomous refresh of floating body cell (FBC)
-
Dec
-
T. Ohsawa, R. Fukuda, T. Higashi, K. Fujita, F. Matsuoka, T. Shino, H. Furuhashi, Y. Minami, H. Nakajima, T. Hamamoto, Y. Watanabe, A. Nitayama, and T. Furuyama, "Autonomous refresh of floating body cell (FBC)," in IEDM Tech. Dig., Dec. 2008, pp. 801-804.
-
(2008)
IEDM Tech. Dig
, pp. 801-804
-
-
Ohsawa, T.1
Fukuda, R.2
Higashi, T.3
Fujita, K.4
Matsuoka, F.5
Shino, T.6
Furuhashi, H.7
Minami, Y.8
Nakajima, H.9
Hamamoto, T.10
Watanabe, Y.11
Nitayama, A.12
Furuyama, T.13
-
13
-
-
0036575333
-
Principles of transient charge pumping on partially depleted SOI MOSFETs
-
May
-
S. Okhonin, M. Nagoga, and P. Faza, "Principles of transient charge pumping on partially depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 23, no. 5, pp. 279-281, May 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.23
, Issue.5
, pp. 279-281
-
-
Okhonin, S.1
Nagoga, M.2
Faza, P.3
-
14
-
-
57749197395
-
Array architecture of floating body cell (FBC) with quasishielded open bit line scheme for sub-40 nm node
-
Oct
-
K. Fujita, T. Ohsawa, R. Fukuda, F. Matsuoka, T. Higashi, T. Shino, and Y. Watanabe, "Array architecture of floating body cell (FBC) with quasishielded open bit line scheme for sub-40 nm node," in Proc. IEEE Int. SOI Conf., Oct. 2008, pp. 31-32.
-
(2008)
Proc. IEEE Int. SOI Conf
, pp. 31-32
-
-
Fujita, K.1
Ohsawa, T.2
Fukuda, R.3
Matsuoka, F.4
Higashi, T.5
Shino, T.6
Watanabe, Y.7
-
15
-
-
0024684383
-
A new static memory cell based on the reverse base current effect of bipolar transistor
-
Jun
-
K. Sakui, T. Hasegawa, T. Fuse, S. Watanabe, K. Ohuchi, and F. Masuoka, "A new static memory cell based on the reverse base current effect of bipolar transistor," IEEE Trans. Electron Devices, vol. 36, no. 6, pp. 1215-1217, Jun. 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, Issue.6
, pp. 1215-1217
-
-
Sakui, K.1
Hasegawa, T.2
Fuse, T.3
Watanabe, S.4
Ohuchi, K.5
Masuoka, F.6
-
16
-
-
39749187678
-
Thyristor-based volatile memory in nano-scale CMOS
-
Feb
-
R. Roy, F. Nemati, K. Young, B. Bateman, R. Chopra, S.-O. Jung, C. Show, and H.-J. Cho, "Thyristor-based volatile memory in nano-scale CMOS," in Proc. ISSCC Dig. Tech. Papers, Feb. 2006, pp. 632-633.
-
(2006)
Proc. ISSCC Dig. Tech. Papers
, pp. 632-633
-
-
Roy, R.1
Nemati, F.2
Young, K.3
Bateman, B.4
Chopra, R.5
Jung, S.-O.6
Show, C.7
Cho, H.-J.8
-
17
-
-
70350047997
-
Highly scalable Z-RAM with remarkably long data retention for DRAM application
-
Jun
-
T.-S. Jang, J.-S. Kim, S.-M. Hwang, Y.-H. Oh, K.-M. Rho, S.-J. Chung, S.-O. Chung, J.-G. Oh, S. Bhardwaj, J. Kwon, D. Kim, M. Nagoga, Y.-T. Kim, S.-Y. Cha, S.-C. Moon, S.-W. Chung, S.-J. Hong, and S.-W. Park, "Highly scalable Z-RAM with remarkably long data retention for DRAM application," in VLSI Symp. Tech. Dig., Jun. 2009, pp. 234-235.
-
(2009)
VLSI Symp. Tech. Dig
, pp. 234-235
-
-
Jang, T.-S.1
Kim, J.-S.2
Hwang, S.-M.3
Oh, Y.-H.4
Rho, K.-M.5
Chung, S.-J.6
Chung, S.-O.7
Oh, J.-G.8
Bhardwaj, S.9
Kwon, J.10
Kim, D.11
Nagoga, M.12
Kim, Y.-T.13
Cha, S.-Y.14
Moon, S.-C.15
Chung, S.-W.16
Hong, S.-J.17
Park, S.-W.18
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