A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 460-462

  Singh, Anant ^a   Ciraula, Michael ^b   Weiss, Don ^b   Wuu, John ^b   Bauser, Philippe ^a   De Champs, Paul ^a   Daghighian, Hamid ^a   Fisch, David ^a   Graber, Philippe ^a   Bron, Michel ^a  

^a Innovative Silicon   (Switzerland)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349291207     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977507     Document Type: Conference Paper

References (5)

1. T. Ohsawa, K. Fujita, K. Hatsuda, et al., "An 18.5ns 128Mb SOI DRAM with a Floating Body Cell", ISSCC Dig. Tech. Papers, pp. 458- 609, Feb.2005.
2. F. Morishita, I Hayashi, T. Gyohten, et al., "A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory", IEEE J. Solid State Circuits, vol.42, no.4, pp. 853-861, April 2007.
3. S. Okhonin, M. Nagoga, E. Carman, et al., "New Generation of Z-RAM", IEDM, pp. 925- 928, Dec. 2007.
4. J. Barth, W. Reohr, P. Parries, et al., "A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring A 3T Micro Sense Amplifier", ISSCC Dig. Tech. Papers, pp. 486-487, Feb. 2007.
5. H. Pilo, V. Ramadurai, G. Braceras, et al., "A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management", ISSCC Dig. Tech. Papers, pp. 378-379, Feb. 2008.