A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

IEEE Transactions on Electron Devices

Volumn 54, Issue 3, 2007, Pages 563-571

  Hamamoto, Takeshi ^a   Minami, Yoshihiro ^a   Shino, Tomoaki ^a   Kusunoki, Naoki ^a   Nakajima, Hiroomi ^a   Morikado, Mutsuo ^a   Yamada, Takashi ^a   Inoh, Kazumi ^a   Sakamoto, Atsushi ^a   Higashi, Tomoki ^a   Fujita, Katsuyuki ^a   Hatsuda, Kozuke ^a   Ohsawa, Takashi ^a   Nitayama, Akihiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

DRAM chips; Hot carriers; MOSFETs; Silicon on insulator (SOI) technology

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; HOT CARRIERS; MOSFET DEVICES; SCALABILITY; SILICON ON INSULATOR TECHNOLOGY;

COMPATIBILITY; FLOATING-BODY CELL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 33947625047     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.890597     Document Type: Article

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