Design of a 128-mb SOI DRAM using the floating body cell (FBC)

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 135-145

  Ohsawa, T ^a   Fujita, K ^a   Hatsuda, K ^a   Higashi, T ^a   Shino, T ^a   Minami, Y ^a   Nakajima, H ^a   Morikado, M ^a   Inoh, K ^a   Hamamoto, T ^a   Watanabe, S ^a   Fujii, S ^a   Furuyama, T ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

128 Mbit; Charge pumping; DRAM robustness; Dummy cells; Floating body cell; Monte Carlo simulation; Multi pair averaging; Quasi nondestructive read out; Redundancy; Sense amplifier; Silicon on insulator technology; SOI DRAM; Word line disturb

Indexed keywords

COMPUTER SIMULATION; MONTE CARLO METHODS; POWER AMPLIFIERS; READOUT SYSTEMS; REDUNDANCY; SILICON ON INSULATOR TECHNOLOGY;

128 MBIT; DRAM ROBUSTNESS; DUMMY CELLS; FLOATING BODY CELL; MULTI-PAIR AVERAGING; QUASI-NONDESTRUCTIVE READ-OUT; SENSE AMPLIFIER; SILICON-ON-INSULATOR TECHNOLOGY; SOI DRAM; WORD-LINE DISTURB;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 31344475509     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.0051.859018     Document Type: Article

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