Memory design using one-transistor gain cell on SOI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 152-153+454+151

  Ohsawa, Takashi ^a   Fujita, Katsuyuki ^a   Higashi, Tomoki ^a   Iwata, Yoshihisa ^a   Kajiyama, Takeshi ^a   Asao, Yoshiaki ^a   Sunouchi, Kazumasa ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; FERMI LEVEL; MOS DEVICES; THRESHOLD VOLTAGE; TRANSISTORS;

FLOATING BODY TRANSISTOR CELLS (FBC);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036104766     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Phase-state Low Electron-number Drive Random Access Memory(PLEDM)
2. A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell
3. A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM