Floating body RAM technology and its scalability to 32nm node and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Shino, Tomoaki ^a   Kusunoki, Naoki ^a   Higashi, Tomoki ^a   Ohsawa, Takashi ^a   Fujita, Katsuyuki ^a   Hatsuda, Kosuke ^a   Ikumi, Nobuyuki ^a   Matsuoka, Fumiyoshi ^a   Kajitani, Yasuyuki ^a   Fukuda, Ryo ^a   Watanabe, Yoji ^a   Minami, Yoshihiro ^a   Sakamoto, Atsushi ^a   Nishimura, Jun ^a   Nakajima, Hiroomi ^a   Morikado, Mutsuo ^a   Inoh, Kazumi ^a   Hamamoto, Takeshi ^a   Nitayama, Akihiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; NANOTECHNOLOGY; RANDOM ACCESS STORAGE; TECHNOLOGY;

CHIP YIELD; DATA RETENTION TIME; DEVICE SIMULATIONS; FLOATING BODIES; IMPROVED PERFORMANCE; SOI THICKNESS; VOLTAGE DIFFERENCE;

BODIES OF REVOLUTION;

EID: 46049102832     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346846     Document Type: Conference Paper

References (4)

1. T. Ohsawa, et al., "A 128Mb Floating Body RAM (FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell", in Symp. on VLSI Circuits Dig., Jun. 2006, pp.224-225.
2. Y. Minami, et al., "A Floating Body Cell (FBC) Fully Compatible with 90nm CMOS Technology (CMOSIV) for 128Mb SOI DRAM", in IEDM Tech. Dig., 2005, pp.317-320.
3. K. Hatsuda, K. Fujita and T. Ohsawa, "A 333MHz Random Cycle DRAM Using the Floating Body Cell", in Proc. IEEE Custom Integrated Circuits Conference, 2005, pp.259-262.
4. T. Hamamoto, et al., submitted to IEEE Trans. Electron Devices.