Serial-link bus: A low-power on-chip bus architecture

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 9, 2009, Pages 2020-2032

  Ghoneima, Maged ^a   Ismail, Yehea ^b   Khellah, Muhammad M ^c   Tschanz, James ^c   De, Vivek ^c  

^a NVIDIA   (United States)

^b Northwestern University   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Coupling capacitance; Low power; On chip buses; On chip interconnect; Serial link

Indexed keywords

CAPACITANCE; ENERGY DISSIPATION; PARALLEL ARCHITECTURES;

COUPLING CAPACITANCE; LOW POWER; ON CHIP INTERCONNECT; ON-CHIP BUS; SERIAL LINK;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 70349254176     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2010155     Document Type: Article

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