Interconnect sizing and spacing with consideration of coupling capacitance

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 9, 2001, Pages 1164-1169

  Cong, Jason ^a   He, Lei ^b   Koh, Cheng Kok ^c   Pan, Zhigang ^d  

^a University of California   (United States)

^b University of Wisconsin Madison   (United States)

^c Purdue University   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Coupling capacitance; Interconnect; Wire sizing; Wire spacing

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTATIONAL METHODS; ELECTRIC RESISTANCE; ELECTRIC WIRE; OPTIMIZATION;

SUBMICROMETER DESIGN; WIRE SIZING; WIRE SPACING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035439983     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.945311     Document Type: Article

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