A transition-encoded dynamic bus technique for high-performance interconnects

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 5, 2003, Pages 709-714

  Anders, Mark ^a   Rai, Nivruti ^a   Krishnamurthy, Ram K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Coupling capacitance; Dynamic circuits; On chip interconnects; Transition encoding

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PERFORMANCE; THRESHOLD VOLTAGE;

COUPLING CAPACITANCE; DROP-IN REPLACEMENT; DYNAMIC BUS TECHNIQUE; TRANSITION ENCODING;

INTERCONNECTION NETWORKS;

EID: 0038529371     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.810061     Document Type: Article

References (6)

1. J.A. Davis et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, pp. 305-324, Dec. 2001.
2. M. T. Bohr, "Interconnect scaling - The real limiter to high performance ULSI," in Proc. IEEE Electron Devices Meeting, 1995, pp. 241-244.
3. M. Anders, N. Rai, R. Krishnamurthy, and S. Borkar, "A transition-encoded dynamic bus technique for high-performance interconnects," in Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp. 16-17.
4. M. R. Stan and W. P. Burleson, "Low-power encodings for global communications in CMOS VLSI," IEEE Trans. VLSI Syst., vol. 5, pp. 444-454, Dec. 1997.
5. S. Tyagi et al., "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors, and 6 layers of Cu interconnects," in Proc. IEEE Electron Devices Meeting, 2000, pp. 567-570.
6. G. Hinton et al., "A 0.18 μm CMOS IA-32 processor with a 4-GHz integer execution unit," IEEE J. Solid-State Circuits, vol. 36, pp. 324-325, Nov. 2001.