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Volumn , Issue , 2008, Pages 77-83

Low power and reliable interconnection with self-corrected green coding scheme for network-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY REDUCTION; NANOSCALE TECHNOLOGY; NETWORK-ON-CHIPS;

EID: 44149125102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492727     Document Type: Conference Paper
Times cited : (22)

References (10)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on Chips: A New SoC Paradigm
    • Jan
    • L. Benini and G. De-Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, vol. 35, pp. 70-78, Jan. 2002.
    • (2002) IEEE Computer , vol.35 , pp. 70-78
    • Benini, L.1    De-Micheli, G.2
  • 2
    • 44149092973 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors, http:// public.itrs.net, 2005 - 2007.
    • (2005)
  • 4
    • 23744468720 scopus 로고    scopus 로고
    • S.R. Sridhara, et al., Coding for System-on-Chip Networks: A Unified Framwork,IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 13, No. 8, pp. 655-667, Jun. 2005.
    • S.R. Sridhara, et al., "Coding for System-on-Chip Networks: A Unified Framwork,"IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 13, No. 8, pp. 655-667, Jun. 2005.
  • 5
    • 34248590882 scopus 로고    scopus 로고
    • Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
    • May
    • S.R. Sridhara, et al., "Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.26, pp. 977-582, May. 2007.
    • (2007) IEEE Trans. on CAD of Integrated Circuits and Systems , vol.26 , pp. 977-582
    • Sridhara, S.R.1
  • 6
    • 38749126805 scopus 로고    scopus 로고
    • Design of Low power & Reliable Netoworks on Chip through joint crosstalk avoidance and forward error correction coding
    • Oct
    • P.P. Panda et al., "Design of Low power & Reliable Netoworks on Chip through joint crosstalk avoidance and forward error correction coding," IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 466-476, Oct. 2006.
    • (2006) IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems , pp. 466-476
    • Panda, P.P.1
  • 7
    • 44149113383 scopus 로고    scopus 로고
    • Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding
    • Mar
    • A. Ganguly et al., "Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding ," IEEE Symposium on computer society Annual, pp. 799-808, Mar. 2007.
    • (2007) IEEE Symposium on computer society Annual , pp. 799-808
    • Ganguly, A.1
  • 8
    • 2442698800 scopus 로고    scopus 로고
    • A 51mW 1.6GHz On-Chip Network for Low Power Heterogeneous SoC Platform
    • Feb
    • K. Lee et al., "A 51mW 1.6GHz On-Chip Network for Low Power Heterogeneous SoC Platform," IEEE International Solid-State Circuits Conference, pp. 152-153, Feb. 2004.
    • (2004) IEEE International Solid-State Circuits Conference , pp. 152-153
    • Lee, K.1
  • 9
    • 27344452711 scopus 로고    scopus 로고
    • Se-Joong Lee, Kangmin. Lee and Hoi-Jun Yoo, Analysis and Implemenation of Practical, Cost-Effective Networks on Chips, IEEE Design & Test Computers, 22, pp. 422-433, 2005.
    • Se-Joong Lee, Kangmin. Lee and Hoi-Jun Yoo, " Analysis and Implemenation of Practical, Cost-Effective Networks on Chips," IEEE Design & Test Computers, Vol. 22, pp. 422-433, 2005.
  • 10
    • 44149100123 scopus 로고    scopus 로고
    • A 5.2mW All-Digital Fast-Lock Self- Calibrated Multiphase DLL
    • to be published in
    • L.P. Chuang, et al., "A 5.2mW All-Digital Fast-Lock Self- Calibrated Multiphase DLL," to be published in International Symposium on Circuits and Systems, 2008.
    • (2008) International Symposium on Circuits and Systems
    • Chuang, L.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.