Combining wire swapping and spacing for low-power deep-submicron buses

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 198-202

  Macii, Enrico ^a   Poncino, Massimo ^b   Salerno, Sabino ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF VERONA   (Italy)

Author keywords

Bus Encoding; Crosstalk; Low Power Design; Physical Design

Indexed keywords

CROSSTALK; ELECTRIC LOSSES; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); ROUTERS; SWITCHING; WIRE;

BUS ENCODING;

COMPUTER CIRCUITS;

EID: 0038375770     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764856.764859     Document Type: Conference Paper

References (9)

1. P.P. Sotiriadis, A. Chandrakasan, "Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep SubMicron Technologies," ICCAD'00, pp. 322-327, Nov. 2000.
2. 2BC: Adaptive Address Bus Coding for Low-Power Deep Sub-Micron Designs," 38th DAC, pp. 744-749, June 2001.
3. K.-W. Kim, K.-H. Baek, N. Shanbag, C.L. Liu, S.-M. Kang, "Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design", ICCAD'00, pp. 317-321, Nov. 2000.
4. B. Victor, K. Keutzer, "Bus Encoding to Prevent Crosstalk Delay", ICCD'01, pp. 57-63, Nov. 2001.
5. L. Macchiarulo, E. Macii, M. Poncino, "Low-Energy Encoding for Deep-Submicron Address Buses," ISLPED'01, pp. 176-181, August 2001.
6. Y. Shin, T. Sakurai, "Coupling-Driven Bus Design for Low-Power Application-Specific Systems", 38th DAC, pp. 750-753, June 2001.
7. S.P. Khatri, A. Mehrotra, R.K. Brayton, R.H.J.M. Otten, A. Sangiovanni-Vincentelli "A novel VLSI layout fabric for deep sub-micron applications" 36th DAC, pp. 491-496, June 1999.
8. L. Macchiarulo, E. Macii, M. Poncino, "Wire Placement for Crosstalk Energy Minimization in Address Buses," DATE'02, pp. 158-162, Mar. 2002.
9. K. Nahors, J. White, "FastCap: a Multi-pole Accelerated 3-D Capacitance Extraction Program", IEEE Transactions on CAD, 10(11), pp. 1447-1459, Nov. 1991.