A skewed repeater bus architecture for on-chip energy reduction in microprocessors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 253-257

  Khellah, Muhammad ^a   Ghoneima, Maged ^b   Tschanz, James ^a   Ye, Yibin ^a   Kurd, Nasser ^a   Barkatullah, Javed ^a   Nimmagadda, Srikanth ^a   Ismail, Yehea ^b   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

^b NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAYED CLOCK BUS (DCB); DELAYED DATA BUS (DDB); ENERGY REDUCTION; SKEWED REPEATER BUS (SRB);

COMPUTER SIMULATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS;

COMPUTER ARCHITECTURE;

EID: 33748550292     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.14     Document Type: Conference Paper

References (4)

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3. K. Nose, and T. Sakurai, "Two schemes to reduce interconnect delays in bi-directional and uni-directional buses," Symposium on VLSI Circuits, 2001, pp. 193-194.
4. K. Hirose and H. Yasuura, "A bus delay reduction technique considering crosstalk," Proc. of DATE, 2000, pp.441-445.