On real-time AER 2-D convolutions hardware for neuromorphic spike-based cortical processing

IEEE Transactions on Neural Networks

Volumn 19, Issue 7, 2008, Pages 1196-1219

  Serrano Gotarredona, Rafael ^a,b   Serrano Gotarredona, Teresa ^a   Acosta Jiménez, Antonio ^a   Serrano Gotarredona, Clara ^a   Pérez Carrasco, José A ^a   Linares Barranco, Bernabé ^a,c   Linares Barranco, Alejandro ^c   Jiménez Moreno, Gabriel ^c   Civit Ballcels, Antón ^c  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

^b NXP Semiconductors Austria GmbH   (Austria)

^c UNIVERSITY OF SEVILLE   (Spain)

Author keywords

Address event representation (AER); Analog circuits; Asynchronous circuits; Bioinspired systems; Cortical layer processing; Image convolutions; Image processing; Low power circuits; Mixed signal circuits; Spike based processing

Indexed keywords

ARSENIC COMPOUNDS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEMS; CONVOLUTION; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; FUNCTIONS; INTERFACES (COMPUTER); METALS; NETWORKS (CIRCUITS); NEURAL NETWORKS; OPTICAL DESIGN; STANDARDS; VIDEO RECORDING;

ADDRESS-EVENT REPRESENTATION (AER); ARBITRARY SHAPES; BIOLOGICALLY INSPIRED; CIRCUIT TECHNIQUES; COMMUNICATION BAND WIDTH; COMPUTER INTERFACING; CONVENTIONAL COMPUTERS; CORTICAL PROCESSING; FABRICATED CHIPS; KERNEL SIZE; LOW CURRENT (ITC); LOW POWERS; METAL-OXIDE SEMICONDUCTOR (MOS); MISMATCH CALIBRATION; MULTILAYER (ML); NANOAMPERES; NEUROMORPHIC; PICOAMPERES; PIXEL ARRAYS; PIXEL LEVEL; PROGRAMMABLE KERNELS; REAL-TIME IMAGING; REDUCED SIZE; SCALING-UP; SYSTEM LEVELS; VIDEO REPRESENTATIONS;

PIXELS;

EID: 48949116215     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2008.2000163     Document Type: Article

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